From patchwork Tue Aug 20 05:57:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 820852 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 230B415C13C; Tue, 20 Aug 2024 05:57:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724133474; cv=none; b=NFsSyXlFYXQuD9ckE54duOmEeXDeVMhO8j5ZC7Wkks44867yA4emxyZZuHUNoCvLoKdxFohPoc/fwMw4dtC35LSYyV10aIwdvrJBxB0dFelZsOJ0vSgzgSx3C89/EGofj9eW9PmlXF7nlyRvOezjTGc4TjnThw4J/VOGJQPow7E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724133474; c=relaxed/simple; bh=wdrkuJwvNKQsERO7MDEJmd26F8IvwANIcKphR1lddWM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GDKJv+nqOZ/oylTxZz8KKrxAPIhoTz6dhX7IX0J0TT8Vh24K/GB8gmfeTEF9TFKR3jMYUul/QAM3OMxK9A/zme33qCxNz/4O2+b2htlZtJ3lobY5uCIXWlLJhI5lJigeCJhdQEzyM0cOW+Cp18DJH3qltnAVBfDZHRV1RLjfn+Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=myGt1hyX; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="myGt1hyX" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 47JN1ZeV025154; Tue, 20 Aug 2024 05:57:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pM72EZFISFh3f+XiZ8pWoOy2vxtAbU6yWL4FU7RDmX4=; b=myGt1hyXyS/raR+m Mr1qVAvKyvVTND8naQyXmQVGR8vFm0kYr4nIP0Qk6p4aDxROgZ8synAs7ge0Wb3D H4SGqBXaiw9SRgRXykLspfeYJQhwBj0Lzl9wbomyvfLaEK1ptbY4rXmrFh6J/hdz dkVroEs1eoArkSlaxAUXCfpE5aC+6ulMBIcVRNbRM5NywJpkSreDMxwjR6vn/aIL n4S5l4+WMU8LkSxzlHzso0tXs7KZbxxzxTdIIYpaDqlMl6LkDV9DQ/6q+GtyLaMI HUDlAsJdh9ay3pAkHxt1s7uAa0RVrVEAxHhf1Ywf6a3gblZ2in1mEPfUKXnXzhoJ qFbUTQ== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 412m32pfa1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Aug 2024 05:57:49 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47K5vnLi027451 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Aug 2024 05:57:49 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 19 Aug 2024 22:57:44 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , CC: Varadarajan Narayanan , Dmitry Baryshkov Subject: [PATCH v7 5/7] clk: qcom: gcc-ipq9574: Add CPR clock definition Date: Tue, 20 Aug 2024 11:27:03 +0530 Message-ID: <20240820055705.3922754-6-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240820055705.3922754-1-quic_varada@quicinc.com> References: <20240820055705.3922754-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: FLwOJcUzX6eqepZtRVt6XvJ9M65E7ZrH X-Proofpoint-ORIG-GUID: FLwOJcUzX6eqepZtRVt6XvJ9M65E7ZrH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-19_16,2024-08-19_03,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 suspectscore=0 priorityscore=1501 phishscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 mlxlogscore=999 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408200044 Add the CPR clock definition needed for enabling access to CPR register space. Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan --- drivers/clk/qcom/gcc-ipq9574.c | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 80fc94d705a0..058cde71b202 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -3997,6 +3997,43 @@ static struct clk_branch gcc_xo_div4_clk = { }, }; +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { + F(24000000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 rbcpr_clk_src = { + .cmd_rcgr = 0x48044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_xo_map, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rbcpr_clk_src", + .parent_data = gcc_xo_gpll0_gpll4, + .num_parents = ARRAY_SIZE(gcc_xo_map), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_rbcpr_clk = { + .halt_reg = 0x48008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x48008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rbcpr_clk", + .parent_hws = (const struct clk_hw *[]) { + &rbcpr_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_hw *gcc_ipq9574_hws[] = { &gpll0_out_main_div2.hw, &gcc_xo_div4_clk_src.hw, @@ -4222,6 +4259,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr, [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr, + [GCC_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, + [GCC_RBCPR_CLK] = &gcc_rbcpr_clk.clkr, }; static const struct qcom_reset_map gcc_ipq9574_resets[] = {