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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v2 11/13] x86/process: Clear hardware feedback history for AMD processors Date: Thu, 10 Oct 2024 14:37:03 -0500 Message-ID: <20241010193705.10362-12-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241010193705.10362-1-mario.limonciello@amd.com> References: <20241010193705.10362-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CA:EE_|SA1PR12MB7175:EE_ X-MS-Office365-Filtering-Correlation-Id: a1071107-5749-43ec-3008-08dce9630874 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: 5vUuDEVW5M+9u4+LIAaZNJQB1TBRQH8bSKmjTWpL9gxBUtW3z/1ng4+8ur9gcZWLlNAq3v96KJOaZ+DIuZRIf2gSwrK1i5cq/pYy9xMcxOc+ekdwOJXt8jdyrCMtTXgVrbnPtLylPbloyjIzqPR/6nmksOGAWaGNBDqZ1P08TkHVRV66VWvgnLJGxvj2IVbTFlmA2fGWafodGV7MDBzv6W+BDx/zC5Fikcalx2+oeMTXf611YrBzAqQkIkVpWAtCiEO7jaZczgIEsO9NkpEO7t406yaUN2MUC2TH3ObQ1/UF2Fvzrz3m/GvwNRfG/vqujUZRyDFdstGsz8QhFjq6ihxlfsXAA1Els9jJ01dlo2y236DdBmx3Zepuc/Bp2mZHpqS/BtCPFIGxJH6SehoDtcL43c/3+T7tVfxTDww29vgS2/w8AAyebXm7eknS72/hfDj2oKS6XDFV5GBHOGCf+bOZaYsBtXHWOtV8yTPwgcOibfI8GK3dtfwfmCQc+o3pU4CRf28+jMnnWnHqzbSE6BD7kjjmjOgH3zQaumyx86SyP+sB09yhDjqGfRXSP1AxBuMbKoAw4d50v6bc2NTemaPrTHFoWxMUTkAEgKA/KCrlWauBY1nVbUUu1u+WFG39z7/jQAB+EfD5tFtk8BH3u2L/tIKXXrzKcTZq1NjPuN+hdmb8C4/tofEDpBxWqeg41NaApuDzC3/T17y0ZceCLJ4/5fAlMLRzMRyOuj9InZqB6wrlkGpRwSMbwfFEE9T1xIoNMDM5+L2WSy5taFnUA1uAu5rMLNq1LK/jDHuznoF9DGCYVEomyZmKMzh/DH2PZEA0lIhide90Vf0xlhHI2tP08K/8n4TbtZ3Ntwlk/xgU/L+r/ipJ+ELGT9EIBx9AZ17miAgmoh2d6nFcwj1JgUUMW8T7dFud7Ll0TktaEexqtRjz5NeLXMpbpIFQx5LwZ/QJonrzzjm2EDn4DJqxycjpOZZYMSGYP6xNgX3zi8EZp/DGL7BIqRLpyG/k8qh2mZ4LywBh6Yk3R3rcA2ZBajZRNWcPdHXleHRrf8EHN3mJIW9nwH6PM4dZUZhLozfsdUkqcwX3DuymZxt3skuBbZ3SaciT1uA02AXJBhFDfRl4WHe8H/S8ah+aD8OhSMX4RAV5iTTrT2ZUxZpb5R5rVVbBLr2IAfHNFu2uJjtero6eUlA8j/GWBxE1twvdTUZAUP0gw03nDyzh5v1vZzd/icxfjq6lIUFguNRx/3qMAw6oFAT73DzUKRtr7OO2u5s/z4jrB736C+2ZBGXE5JXv1ZMuF0j4JDv0DEjH2W7DyoN1VSH1ye8JzepsFuYiICNUvQVDYwBT8IExaKf9MX9nIoZvCbRkppCJeiFCoi7J8xtFsVtgCMhHejFtO5QRJiFa X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2024 19:37:53.0602 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1071107-5749-43ec-3008-08dce9630874 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7175 From: Perry Yuan Incorporate a mechanism within the context switching code to reset the hardware history for AMD processors. Specifically, when a task is switched in, the class ID was read and reset the hardware workload classification history of CPU firmware and then it start to trigger workload classification for the next running thread. Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v2: * Fix function name * Use static keys --- arch/x86/include/asm/hreset.h | 6 ++++++ arch/x86/kernel/cpu/common.c | 15 +++++++++++++++ arch/x86/kernel/process_32.c | 3 +++ arch/x86/kernel/process_64.c | 3 +++ 4 files changed, 27 insertions(+) create mode 100644 arch/x86/include/asm/hreset.h diff --git a/arch/x86/include/asm/hreset.h b/arch/x86/include/asm/hreset.h new file mode 100644 index 000000000000..ae1f72602bbd --- /dev/null +++ b/arch/x86/include/asm/hreset.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_HRESET_H + +void reset_hardware_history_hetero(void); + +#endif /* _ASM_X86_HRESET_H */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 07a34d723505..887821e97e54 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include #include @@ -403,6 +404,7 @@ static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_C X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED; static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); static unsigned long cr4_pinned_bits __ro_after_init; +static DEFINE_STATIC_KEY_FALSE_RO(hardware_history_features); void native_write_cr0(unsigned long val) { @@ -481,6 +483,12 @@ void cr4_init(void) this_cpu_write(cpu_tlbstate.cr4, cr4); } +static void __init setup_hreset(struct cpuinfo_x86 *c) +{ + if (cpu_feature_enabled(X86_FEATURE_WORKLOAD_CLASS)) + static_key_enable_cpuslocked(&hardware_history_features.key); +} + /* * Once CPU feature detection is finished (and boot params have been * parsed), record any of the sensitive CR bits that are set, and @@ -1844,6 +1852,7 @@ static void identify_cpu(struct cpuinfo_x86 *c) setup_smep(c); setup_smap(c); setup_umip(c); + setup_hreset(c); /* Enable FSGSBASE instructions if available. */ if (cpu_has(c, X86_FEATURE_FSGSBASE)) { @@ -2410,3 +2419,9 @@ void __init arch_cpu_finalize_init(void) */ mem_encrypt_init(); } + +__always_inline void reset_hardware_history_hetero(void) +{ + if (static_branch_unlikely(&hardware_history_features)) + wrmsrl(AMD_WORKLOAD_HRST, 0x1); +} diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c index 0917c7f25720..6a3a1339f7a7 100644 --- a/arch/x86/kernel/process_32.c +++ b/arch/x86/kernel/process_32.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include "process.h" @@ -213,6 +214,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + reset_hardware_history_hetero(); + return prev_p; } diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 226472332a70..ea7f765c6262 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -54,6 +54,7 @@ #include #include #include +#include #include #include #include @@ -709,6 +710,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p) /* Load the Intel cache allocation PQR MSR. */ resctrl_sched_in(next_p); + reset_hardware_history_hetero(); + return prev_p; }