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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v3 10/14] x86/cpu: Enable SD_ASYM_PACKING for DIE Domain on AMD Processors Date: Tue, 15 Oct 2024 16:36:41 -0500 Message-ID: <20241015213645.1476-11-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015213645.1476-1-mario.limonciello@amd.com> References: <20241015213645.1476-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0DF:EE_|SJ2PR12MB8009:EE_ X-MS-Office365-Filtering-Correlation-Id: b10e290c-36d3-43d2-72fb-08dced61941a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: k20T/E790ErMiOSNYuA3bM4JhcyCfQL7ks996Q+pz+YinZaepy1xdoH7z/v2CQmhadE6+asb0rxfYeI4IlrCh4jRqMPKov9XphKVZSgbxfba4urvConqM/lIjwwqXO8tSoNf4IIuHuqzA5cVNPsEqbDgtKx+d5LmMEr7mEBlcmtoHJUs00wpJtyPZQS+bHzx60YHtbs27zEA98OHYSan+S2HU8JpIf/JEQ3z54Na6zocJjo4+AYajZJiFr9F4FDf4JU2dewTl4CW3tTl5EHW/NKcQcQa+8rST6C1JQ0aG7z1hN7UT2ReqPix/HpVTgJQiJA3Ts9P0ddceoauv0prIrB4vfgoNQndJd7vz7J03Z8ne4N0W/odZgCPk/44BpSrrYPRZfrgTRG20C/+SEU2UJZLpVCeTQnL3SHh5cll324+jUSS+rlO1G1Nndx3PPqLLJDy4HVmLs2y3ownrpf0EHH5rfLj2EqN71YqJLSzK+eQNYrKfCH15/qL1N092hFnq6hFbvklL3X3Y2UaII4V72col907t62L3uzpD+j0RfDCSZ3jfMVSrw/IF9a6yIz4qzGXz3lqHGxswbzE17BD8386RGXNN7kY0tDIpdyfsVOZQCtx5Q7euHr9o3ULjAA7BmoNhK3sjAKojhcIby/pMiILMQAt8QQ+95Lx0YM9MVZpkyVPeQSULYVTgzMCtL7N7VmzO2yatODw4drzKUT700uZDDuefCgc1LtN0ZS6rzQfPwiQyBWLbCVxMqYQwUbcIPFmQt12d3OBInx9b5hWLLPyyRdAcnkXRQOxCKEaXcBdf0lTyKCHQz1NmQMbd+P/jzCdCkE2DzY5hXz57ide+yWIZBIki4lD923eb3SRt/L+rjOtOgnOBKj1fxBdMfhiO7iWvaNSSosjjpVI0zrnsfCZrv4zW+Dw8uvm9WRNNvOzgjQ19c1p7zGVcl8wZcO6kC/Sb/CrLxnPZdabBzEZldfzDLrP2XOBQQEqQprpChLNFXrBmLOroBLjGHSulUoagP+tv8y1LumveyyYlB//21oexMhM9/QKIJdlWnTa/4I05aJYaPvDiUd+qbGEHQl3MFdMIhk54JU4xEGLw2gx0FGRvVl7AIDL7+QGcVbuVMceYLrtDajyRBO2XGQyuwBrb/9T+bCTXnaluX0X0MULR9NJL0xqboHkY2CRhd6aoJ7/9p7j8U+9h2HEW4tpDgFHS8sxKrmXx9fstSQwAO+YpMogF4vt+PDeo/XRCmav14tfpUHTRzk0K38VQlW2X7AV5ewy9kmbDdE7AlymlHnbbw2MqjmDn4afs12lZ4Mav9UM7h3w9wGLE3QlA9sR2AnPDDnIa4E18XfLV4JX+SIPx/WeFLzaaOBx2ghRckVM7H2iB46WXe3RNWd7MSzf8hHh X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2024 21:37:33.1514 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b10e290c-36d3-43d2-72fb-08dced61941a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8009 From: Perry Yuan Enable the SD_ASYM_PACKING domain flag for the DIE domain on AMD heterogeneous processors. This flag is beneficial for processors with one or more CCDs and relies on x86_sched_itmt_flags(). Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- arch/x86/kernel/smpboot.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 766f092dab80..c01bb75d0375 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -497,8 +497,9 @@ static int x86_cluster_flags(void) static int x86_die_flags(void) { - if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) - return x86_sched_itmt_flags(); + if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU) || + cpu_feature_enabled(X86_FEATURE_HETERO_CORE_TOPOLOGY)) + return x86_sched_itmt_flags(); return 0; }