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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" , Perry Yuan Subject: [PATCH v3 01/14] Documentation: x86: Add AMD Hardware Feedback Interface documentation Date: Tue, 15 Oct 2024 16:36:32 -0500 Message-ID: <20241015213645.1476-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015213645.1476-1-mario.limonciello@amd.com> References: <20241015213645.1476-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E1:EE_|SA3PR12MB8048:EE_ X-MS-Office365-Filtering-Correlation-Id: e44dc336-98ee-400e-c27e-08dced618df8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: 4wbuStg0/upskgQTR146uDdCjtJr2Kvhu8zUTbcDevyldwDabHSsRmBz2UFYC0mc5nxkSjDpFWol8iB5qBb5ksG1iojtCQGv4QvssOr2rLglrJYTVKGfPX3Z3tPtwHidWR5QIa/d8zruot3GxPLReiRpDBcdt0uEnYBHAGXOPHkKrz4fKjYXrPnzLG+DnSV+/R4WXpyi94+YQjVRMBRLTrV5/sUjsHMen+d6mReMQOrcl38nHcN+q+99DZFE6KFcLo55+FTcQ+PPlaHpEjrVAp60/6+qzhQcPMNSrlBlAfLiKCF3pNWOkh243pO3baWRBYlKr0a1+pAJYP3zGjJ4rBrFJB2Rt3fHXK5UFEpoDxWGPbTwuALSRKsqF+yIBAeaRMXLQP7rx96z/MnfVE+FV5cTIrltVRSic5GpAEeLsxSh70g3pbhIXL/5d9YJfaEomEzEF4zp7ioL33j7x/UV0CQK/BhfQl611xNfOWxjGC6wjjgNgMGctzZtF/4GDlZxLlcUwi/ILhdwOp8M1RTLcomZvBZ4dWX+FEcqWB8ojQ3cP0qoPvDfS/tleXvJ/iI1wqYppXsKehpg0SkqsOOOBJeoo/t705cQI75mH5/qreB1eFqxU1RCXoFU/6gsl7mA69o0Qi1yWMieRY54/KHyYpEgGS0m6pCFLKv5jiNTdBFgZ0ViyOly7pOs9kcvCVZboncugTY/stMH1ZGO2KuLzwyHMrwKQjvVX3YSpYpm/hADjqcPDIrrr+Rvb1fvSRLB0dtFUQnKWaIKgviM2YASjTksHzmIgPAWrOG0JXSzcJc/vtLzrBxoXWR1TeYvk9xQQ4yWYV2Bk+/lLoHQWg08GG0WpB/VDjzzCZdIMIcY1aFDRsVyj0n8SKMhBQkVBB+vx9yBOd1cPF5EM3m3GeNXAXS8RAtVJxGyUMgVrzJbtWvC4wDwxOLgPmMLo4YeS5HRLThjfYFW/jhCVBTTf5fD9jyTsV/M3x3uOAe2h2mGvQmDGKOVzLdBumL8d8/kw6ModG9P9VK7FKtDgBOiv5y8tkIhVj+Hq5af8aITn/zUvDS+oXSscGm+OvBvBCOEQNgBmLMu4vXFkXHlpnAtrpLJezyqVvdu+57VKvtV078JXPsqSoe6uThlZJpldp2klQ3QRY/QA1uwp1cfeDs6OI6gxESIpZ/goh26JioVSJU2gjWdvgrZXKb/5ulqWun2gut0bYBfDc6jpYHu3zq5AhGPIpb+DKeqlJxmXlDWD6gDwXxHFyJkDPt/cCZPAd3KfyI5yLJdZWFAVNGp+xsU31zkG7Wqyz+n+u3HJa4zkjbU8tt9NsJEazrCxXRdarfHm3HjaVJg4AXXB4vxdD81aaZM0GdUpBu56V/DjZP/uGP9QQiJ+OJQaO1n3tfjGbls6pOk X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2024 21:37:22.8487 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e44dc336-98ee-400e-c27e-08dced618df8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8048 From: Perry Yuan Introduce a new documentation file, `amd_hfi.rst`, which delves into the implementation details of the AMD Hardware Feedback Interface and its associated driver, `amd_hfi`. This documentation describes how the driver provides hint to the OS scheduling which depends on the capability of core performance and efficiency ranking data. This documentation describes * The design of the driver * How the driver provides hints to the OS scheduling * How the driver interfaces with the kernel for efficiency ranking data. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello Signed-off-by: Mario Limonciello --- v2->v3: * Rewording (Bagas) * Fix toctree entry name (Bagas) --- Documentation/arch/x86/amd-hfi.rst | 115 +++++++++++++++++++++++++++++ Documentation/arch/x86/index.rst | 1 + 2 files changed, 116 insertions(+) create mode 100644 Documentation/arch/x86/amd-hfi.rst diff --git a/Documentation/arch/x86/amd-hfi.rst b/Documentation/arch/x86/amd-hfi.rst new file mode 100644 index 000000000000..2f0d493135c1 --- /dev/null +++ b/Documentation/arch/x86/amd-hfi.rst @@ -0,0 +1,115 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================================================== +Hardware Feedback Interface For Hetero Core Scheduling On AMD Platform +====================================================================== + +:Copyright: 2024 Advanced Micro Devices, Inc. All Rights Reserved. + +:Author: Perry Yuan + +Overview +-------- + +AMD Heterogeneous Core implementations are comprised of more than one +architectural class and CPUs are comprised of cores of various efficiency and +power capabilities: performance-oriented *classic cores* and power-efficient +*dense cores*. As such, power management strategies must be designed to +accommodate the complexities introduced by incorporating different core types. +Heterogeneous systems can also extend to more than two architectural classes as +well. The purpose of the scheduling feedback mechanism is to provide +information to the operating system scheduler in real time such that the +scheduler can direct threads to the optimal core. + +The goal of AMD's heterogeneous architecture is to attain power benefit by sending +background thread to the dense cores while sending high priority threads to the classic +cores. From a performance perspective, sending background threads to dense cores can free +up power headroom and allow the classic cores to optimally service demanding threads. +Furthermore, the area optimized nature of the dense cores allows for an increasing +number of physical cores. This improved core density will have positive multithreaded +performance impact. + +AMD Heterogeneous Core Driver +----------------------------- + +The ``amd_hfi`` driver delivers the operating system a performance and energy efficiency +capability data for each CPU in the system. The scheduler can use the ranking data +from the HFI driver to make task placement decisions. + +Thread Classification and Ranking Table Interaction +---------------------------------------------------- + +The thread classification is used to select into a ranking table that describes +an efficiency and performance ranking for each classification. + +Threads are classified during runtime into enumerated classes. The classes represent +thread performance/power characteristics that may benefit from special scheduling behaviors. +The below table depicts an example of thread classification and a preference where a given thread +should be scheduled based on its thread class. The real time thread classification is consumed +by the operating system and is used to inform the scheduler of where the thread should be placed. + +Thread Classification Example Table +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ++----------+----------------+-------------------------------+---------------------+---------+ +| class ID | Classification | Preferred scheduling behavior | Preemption priority | Counter | ++----------+----------------+-------------------------------+---------------------+---------+ +| 0 | Default | Performant | Highest | | ++----------+----------------+-------------------------------+---------------------+---------+ +| 1 | Non-scalable | Efficient | Lowest | PMCx1A1 | ++----------+----------------+-------------------------------+---------------------+---------+ +| 2 | I/O bound | Efficient | Lowest | PMCx044 | ++----------+----------------+-------------------------------+---------------------+---------+ + + +AMD Hardware Feedback Interface +-------------------------------- + +The Hardware Feedback Interface provides to the operating system information +about the performance and energy efficiency of each CPU in the system. Each +capability is given as a unit-less quantity in the range [0-255]. A higher +performance value indicates higher performance capability, and a higher +efficiency value indicates more efficiency. Energy efficiency and performance +are reported in separate capabilities in the shared memory based ranking table. + +These capabilities may change at runtime as a result of changes in the +operating conditions of the system or the action of external factors. +Power Management FW is responsible for detecting events that would require +a reordering of the performance and efficiency ranking. Table updates would +happen relatively infrequently and occur on the time scale of seconds or more. + +The following events trigger a table update: + * Thermal Stress Events + * Silent Compute + * Extreme Low Battery Scenarios + +The kernel or a userspace policy daemon can use these capabilities to modify +task placement decisions. For instance, if either the performance or energy +capabilities of a given logical processor becomes zero, it is an indication that +the hardware recommends to the operating system to not schedule any tasks on +that processor for performance or energy efficiency reasons, respectively. + +Implementation details for Linux +-------------------------------- + +The implementation of threads scheduling consists of the following steps: + +1. A thread is spawned and scheduled to the ideal core using the default + heterogeneous scheduling policy. +2. The processor profiles thread execution and assigns an enumerated classification ID. + This classification is communicated to the OS via logical processor scope MSR. +3. During the thread context switch out the operating system consumes the workload(WL) + classification which resides in a logical processor scope MSR. +4. The OS triggers the hardware to clear its history by writing to an MSR, + after consuming the WL classification and before switching in the new thread. +5. If due to the classification, ranking table, and processor availability, + the thread is not on its ideal processor, the OS will then consider scheduling + the thread on its ideal processor (if available). + +Ranking Table update +--------------------------- +The power management firmware issues an platform interrupt after updating the ranking +table and is ready for the operating system to consume it. CPUs receive such interrupt +and read new ranking table from shared memory which PCCT table has provided, then +``amd_hfi`` driver parse the new table to provide new consume data for scheduling decisions. + + diff --git a/Documentation/arch/x86/index.rst b/Documentation/arch/x86/index.rst index 8ac64d7de4dc..56f2923f5259 100644 --- a/Documentation/arch/x86/index.rst +++ b/Documentation/arch/x86/index.rst @@ -43,3 +43,4 @@ x86-specific Documentation features elf_auxvec xstate + amd-hfi