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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v3 04/14] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Tue, 15 Oct 2024 16:36:35 -0500 Message-ID: <20241015213645.1476-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241015213645.1476-1-mario.limonciello@amd.com> References: <20241015213645.1476-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E0:EE_|DS0PR12MB7746:EE_ X-MS-Office365-Filtering-Correlation-Id: b70d3ea3-9922-4308-eca7-08dced618fc0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: JS9GLUP885qtJnoCmY6BNmmyyHCUs2KgYWsGjpXGhClAfRySkzJp36GpQITztX9Z43mNmSkSJoQWFYfMoXODmv0TfLJQOY1ekulUB4wp3bYW4ZK06wH1SRJKa8JSo0DsVp25rU2BLDpcuokZa32rwsLF31wp4aAXLvtLEsYxZV/CTUe01bORhsVemN0MmLwQWtGDMcxN5rAzh0t1HWCC+vr/ed9M61Y8Nk3b/dhLypDvZNetZzGELBZaQc32Bnkk52vdJZ0RXzAOH11RS9fHBk/3dT58JscPgrslzrkeyRVrdn+BfZd6IfaYcQti3+1MlklItHYUxD8uthiojb3tRmo93jbPG/SvQsS+JPUe/6rWTxR07mrZsjXHAvEDFZEVpsmBo4zXe8pxN5CWdqvFBITVnLeUXB7SHajxxkMBINhE41WrLQGEkwCX0r83/laiHayScVSrs/8D1sx19rme0sxtD4gGgzbjHx9+diENICkuQZAxAcIXd5SW+dFjc26U+5tDiI53TOWPdU9X2hKf7livUSuOGt7JrCvdtKsMlt7SfAHxt2Rg7G46GKZ3Sb/d224smcmVShVxBdJpEEmaU5KwvWe0dZWmGGRaCTZ8hkwBMW/a6ecLjtA7qSGLndLtQqfyN0i9MXLDM20THaQ7DtoOHX0ECctAq24MpBUovqEvhPw1JD6DXzQrNG3gBm33AhWZ2SQlfFzTgUAj34FYV+v6Foswz9PuqkwK7rE1OQOwPDKNdaKhkv3TkdXnfPcmihbpFBB3M8iY9rOnxT24TL3LjjcaLN5J9uD5ouz8kQpwTPsU7nVK7MAhe8qJpBy7nA4XBwUCBve33ebZAjwcp1qXZiAiMFBOsG7LPer01bOeSYoBdyHMel3/KKr6hCvY0bsJF581zybc2IWe/dreTdml5jc/bz3O8BBMiX1LfvQ54r3Q8VxuuDin3yIRhTLmNUhg8wJ6eEm31W0TL1XlwewLUqndMwrTCE8+IRHWkJlhW+C0+ethTrF8K1/8vMPRLTW4W4j/iqb8XVtQsqGOSbPsPO/5/QknvZgP/Lnrk8N1XRw77tWKcEMBQ/4eHgVwxDYBJE3dkjpJ2jixqPVQ79MFzdXyfHf1YNs7YuybgAZv4fPjvoEEdlxo6ml4xUP0izsqNFNkPl2HZsVob3/B2XuqHbYWTo/AZZ6YtLTHsur3bAzcAIn5RfQMUG+h5cnHayAkpFCq3fx9NR+p+x58Ij/WhZTufpixO+qpSapgAJ+m1//5IWYFEgmt6R6znYLJwMDWtodU8VYUEVN+qxybz9QoTVUEjJpeEy4Yhff5/0ndjKK1cpBjFAj6qfHJQaYNDrw0a+/R+WCcCK/J1Isu2osFfz9vkAo3+3e4qihILbSpa13pQj1stQb/GsWnTNWl X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2024 21:37:25.8382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b70d3ea3-9922-4308-eca7-08dced618fc0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7746 From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 3ae84c3b8e6d..0cd5ffe50f4a 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -712,6 +712,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e