From patchwork Wed Oct 30 13:31:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 839761 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64A931E570E; Wed, 30 Oct 2024 13:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730295136; cv=none; b=ddxPIozIBFuIrSKE+0aBuubpxzpmFBWQATeMOK9w37Of/ul5bYJck+z0qY55QoFKvymnVyWlEmovhmIthJ2V2IBl79pNrzyZs/1Dbba56jnmWkiKTp4nMj8xLGuhJzIA9pZQQIGsM+9pmOjNMsKpaBJ7VLS4MfGuuaKovmversA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730295136; c=relaxed/simple; bh=A3P0x+0FP1lUv1l+YQtrfhbDMMUcog/NdLSQXT0BOoA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Numq2iItOY4titfF7UhNXANbzCcTrpysQ/abvPyVPuZOLZorOmgCWPpttn/rGAAbIZUctvntSjxapvcSublgJAxyjgFIey2+pMEPvst6QdXo5vfrlPh462Miys0vxAlgDvXuoav7x2LOi7T5BWTB+Wn5oLTkn9vcNYxga+prUoA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=mKsRhVIH; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="mKsRhVIH" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49U9x5OJ012773; Wed, 30 Oct 2024 13:32:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= mHQ+Gg6V2ei7AXCu6cKzXPNkuQvbXoSycYg1KOBw+f0=; b=mKsRhVIHXPT4/6OL I7p0NBMHPbrMXFFGwBKseePx36kpeqLmlj1qDyEnpQAF15WBDGuJ9bZ5kXDhD9zB e5AdsHKZbTHS4ZFfkMmVlbb9UcNHWWNMCy8inKHOvAn2yVax/aUAr/WRSUn+3pU9 CO2oD7+7s5iXWXMJAWdcmapuAeuHSNfWx/ziCHEY93K/KmcqGqE0GLOKsRzKfPFG SSo718CEl0DWcW/rQaRITAIHTzNmBYp2OoTNbQ9aRIvKhLcYvYzof49m2CzTlNN6 oa2b8TSO/eZdKvz7uMmap6CQzNOAD+YgGMIR9fAfRdyqxMoAK03cFiJUWY9JgsJj 797/vw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42grgum6jq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Oct 2024 13:32:04 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49UDW3A7024757 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 30 Oct 2024 13:32:03 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 30 Oct 2024 06:31:58 -0700 From: Sibi Sankar To: , , , , , , , , CC: , , , , , Sibi Sankar Subject: [PATCH V6 1/1] cpufreq: scmi: Register for limit change notifications Date: Wed, 30 Oct 2024 19:01:33 +0530 Message-ID: <20241030133133.2932722-2-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241030133133.2932722-1-quic_sibis@quicinc.com> References: <20241030133133.2932722-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: SHu6vOOkDMECajIkn3n51HKE80Eadjy6 X-Proofpoint-GUID: SHu6vOOkDMECajIkn3n51HKE80Eadjy6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 mlxscore=0 bulkscore=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410300106 Register for limit change notifications if supported and use the throttled frequency from the notification to apply HW pressure. Signed-off-by: Sibi Sankar Tested-by: Mike Tipton Reviewed-by: Cristian Marussi Reviewed-by: Lukasz Luba --- v6: * Unregister the notifier in the exit path to make sure the cpus work across suspend/resume cycles. drivers/cpufreq/scmi-cpufreq.c | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/cpufreq/scmi-cpufreq.c b/drivers/cpufreq/scmi-cpufreq.c index 5892c73e129d..fb3534eae722 100644 --- a/drivers/cpufreq/scmi-cpufreq.c +++ b/drivers/cpufreq/scmi-cpufreq.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -25,7 +26,9 @@ struct scmi_data { int domain_id; int nr_opp; struct device *cpu_dev; + struct cpufreq_policy *policy; cpumask_var_t opp_shared_cpus; + struct notifier_block limit_notify_nb; }; static struct scmi_protocol_handle *ph; @@ -174,6 +177,25 @@ static struct freq_attr *scmi_cpufreq_hw_attr[] = { NULL, }; +static int scmi_limit_notify_cb(struct notifier_block *nb, unsigned long event, void *data) +{ + struct scmi_data *priv = container_of(nb, struct scmi_data, limit_notify_nb); + struct scmi_perf_limits_report *limit_notify = data; + struct cpufreq_policy *policy = priv->policy; + unsigned int limit_freq_khz; + int ret; + + limit_freq_khz = limit_notify->range_max_freq / HZ_PER_KHZ; + + policy->max = clamp(limit_freq_khz, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq); + + ret = freq_qos_update_request(policy->max_freq_req, policy->max); + if (ret < 0) + pr_warn("failed to update freq constraint: %d\n", ret); + + return NOTIFY_OK; +} + static int scmi_cpufreq_init(struct cpufreq_policy *policy) { int ret, nr_opp, domain; @@ -181,6 +203,7 @@ static int scmi_cpufreq_init(struct cpufreq_policy *policy) struct device *cpu_dev; struct scmi_data *priv; struct cpufreq_frequency_table *freq_table; + struct scmi_device *sdev = cpufreq_get_driver_data(); cpu_dev = get_cpu_device(policy->cpu); if (!cpu_dev) { @@ -294,6 +317,17 @@ static int scmi_cpufreq_init(struct cpufreq_policy *policy) } } + priv->limit_notify_nb.notifier_call = scmi_limit_notify_cb; + ret = sdev->handle->notify_ops->devm_event_notifier_register(sdev, SCMI_PROTOCOL_PERF, + SCMI_EVENT_PERFORMANCE_LIMITS_CHANGED, + &domain, + &priv->limit_notify_nb); + if (ret) + dev_warn(&sdev->dev, + "failed to register for limits change notifier for domain %d\n", domain); + + priv->policy = policy; + return 0; out_free_opp: @@ -310,8 +344,10 @@ static int scmi_cpufreq_init(struct cpufreq_policy *policy) static void scmi_cpufreq_exit(struct cpufreq_policy *policy) { + struct scmi_device *sdev = cpufreq_get_driver_data(); struct scmi_data *priv = policy->driver_data; + sdev->handle->notify_ops->devm_event_notifier_unregister(sdev, &priv->limit_notify_nb); dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table); dev_pm_opp_remove_all_dynamic(priv->cpu_dev); free_cpumask_var(priv->opp_shared_cpus); @@ -370,6 +406,8 @@ static int scmi_cpufreq_probe(struct scmi_device *sdev) if (!handle) return -ENODEV; + scmi_cpufreq_driver.driver_data = sdev; + perf_ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_PERF, &ph); if (IS_ERR(perf_ops)) return PTR_ERR(perf_ops);