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Shenoy" , "Mario Limonciello" , Perry Yuan , , , , , "Shyam Sundar S K" Subject: [PATCH v6 03/12] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Mon, 4 Nov 2024 11:53:58 -0600 Message-ID: <20241104175407.19546-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241104175407.19546-1-mario.limonciello@amd.com> References: <20241104175407.19546-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002312:EE_|PH7PR12MB8121:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d2dcb76-4aed-440a-007b-08dcfcf9c27a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: OPvs9pwOJzoYpEOor8mAtdHwL8rQOrDZv93Bq+J1DHoLYbyvzJCqg5Kyk1krxGmviqE9FCUlG/4RSWPTSyRxN528f3CBFMFOokOqvj8YzXNWI3psUDCtddcJrfrxjKh1CosS6PwJs14qhWandkhbhhLwZYxM+/zNb3hbBpPsNCHwiXXEYBM2iGwlHKQKEAKJ0SNjE0qLeit/8N3ousYBqZJJfP79u2X9/OAipJNQt6GYUjulWrY+qRhMq+huwIev/evLmt0wr4fjji157dfFbr7e+fitcmgW+A5K0lwitpoW7+CLKjlw6o8m4tyTWyi9BQTrSTO6S28WAkvk/fdmqEj/eVQ5TxU5r5YJEptNiGSBi85Z9Qg2Y4njskVZUZnakU9Tfmm6RkEFjg1iJyO+vzTB4g5IaU2oFLP8DCx0U1kp67quzY4Y5Cr2SwTYaQlQ1uDTP9529VaQpvLO0pw9RqUp9WPxlq5lpjpxHmTjvRYgrlIDZ/MpcAjxzeF+wvZOPAslTPqjjai45RjQh5vgcOKpZwoZ8radEPB4IUL4PBKjC2eMY6ums62oV01tafx/pR/vBsn4p4NRuaVUTm7bT4hLcXHcwJXowa4oAu04PHsruGBg/wyGlSlIMksGEM6K7fGCo2n/Z1QYFYQ5H9ZnPogPXewRz4I7zBtfaDcCIUmFlog7LfrMx6YwTpLqJipxmmYnC0IQDXWRUUZJh9hmY7e65aYISjZJtY+55Tapza4RPWg6/7KxJyQ21drWJUWiDw2klpTCaTw9OZUepYz9noN18wKa+alEiZNwqZkS+PaA86uymwq+i5RYXQU0gGPDwp1r3qm5Eiz17+OzcRLWB6QXRf7+/27I9t1ujSjquEQAm9FrlAG/t7KPYgWTwXdQEkYNxj05WYKAQLKXD7jSYpuzwpZhDIeGQwKrBQUdIfMRddh1RpkNT7FS8j9J+SWPO+PrKj+fPh4z9DSGChhSOQ08yG7QrJjEnSaLKt73vCl577cnIt0R4AAFJZFhXEu8ZK0Q/bMTaxuTWcBbrkBL8fvZ/k9xnESPoyIuEcbrXrLNDL1LrxU2plnWkgx5hbVZCgTjfHKEctHcPDVPpQS406mmHEP/i5Ef5US2SsmbJJKRqNZ1TKDnDT0ptetEvkQ7SFz+M9+bsmGS5aF+43QnmEIKY7bj00qjL4mIqD1mj3qVjooGMfgFVzqXz7t+0f6+QiaXFGFydpLrWz/P6prYN0UiYUly43uNxJtDg3v21PshlEqqmbCi/+plIHlVDMgSXfe29WQGr5vjVHRKZi0wy4craMW8Lq69WRozpfLT0NgXSnOdnnlBrObeeN+RcAk801q703uhwhF/BAGHPdKrZodR/FJg6ONogTrHjkC2wLCXpa78zWzdKjmhlWhJ1xjRhIlzc9UdNZpuEckw72TTBw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2024 17:54:41.8036 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d2dcb76-4aed-440a-007b-08dcfcf9c27a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002312.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8121 From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 3ae84c3b8e6db..0cd5ffe50f4a4 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -712,6 +712,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e