From patchwork Thu Nov 21 18:53:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingwei Zhang X-Patchwork-Id: 844828 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 840FC1E284D for ; Thu, 21 Nov 2024 18:53:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732215233; cv=none; b=daSdsBcUM8kOEBurqIvq64sCrqy1MW00h5Bce7BsESQCS+B4dbVBT9J9uoiWRtM3ngBHjbxpxAWzAuGwoGaU2s7j32rp/JJKywn8FH6b/i1tsUFZHJBQYaL2Ijy753R31jpyO6i4T586WYw8OX1lGzP9Pn1ene6CD0OoUK4+k4M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732215233; c=relaxed/simple; bh=cg2iyp4+CvEy683WYX+ECsqwzXyjhokH3kRioPhRAhA=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=bjVoQXn1m+w3C9h6yD+9+dHX3cAt1hD2CyJWzyiodM+wvJmz500P9sAasAu2iTxO7407skfqQa8PK0DTnAQ2cdZ53kvjtNd4GMip/4y33J01N1g8AsRFwVj8+OA4GN1wDNdWqpwt7EKnb574aKa83LaJdjwrISd9EberWNBes54= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--mizhang.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=j9JoyGno; arc=none smtp.client-ip=209.85.219.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--mizhang.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="j9JoyGno" Received: by mail-yb1-f201.google.com with SMTP id 3f1490d57ef6-e38902a3200so2030786276.2 for ; Thu, 21 Nov 2024 10:53:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1732215230; x=1732820030; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=umjqRaPxMOMBPCY2bbDeorL7OH9qU4LVOhrbwYAX8Gs=; b=j9JoyGnokUtEHz3lfzkhbspaGKCa+33sm0MVSbCDRr0sBQBSR+grVb6mYQDOGsT93f SOx9ViDC28yPoPUAQiNWP/NHAPKgOWxO9kCQ61n7uyeltW42CWGpdbTB+2bOK6r0O/54 O7d6PUgJflGfGf7l2FSbL5+nZ2rG2vHNOxgQCpy/HEKvs5KjDCvVpAouEf6pNEk36pdy NEkeyXWCmQ1WdZmV/YhWg674h4UEqJEFPEhAYFaZL9C67LLyFmAE3eqcjdbWvHDymwZ7 soYq20UQisXLuW4e2dHtz/MIf8wTdYNCV1pzB9enM8ecQOXxF0bxvXKUsI9iz0d2Hx+b iLbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732215230; x=1732820030; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=umjqRaPxMOMBPCY2bbDeorL7OH9qU4LVOhrbwYAX8Gs=; b=eHBZ+0Yt94LOqR+pMgft0Y9rtV2lKoMCG6CCFGm61CRT3CaI4xMDOttCD7k/hYkgbD Wl4xjYSn0sqO12frSAw9okwGdcVz5y/7ebNyh6o/oiJzeSW/biZpTNWPT/PcuXRVm91H PtcTIY1jaKun0qN6mqc3S9sdZo3c9eXWUCcUYX3c1mQq70rpyQgsbFg8ZKA8uR+VAN20 JfMFHTizB0QQcKpvFvoS88oyOUX5BkMse2hihiuPFEc1rDLIRxml5MdRz5AfvbRUGhM1 AL4FSk/hA259MIhpiIqlJLFwBAhlBFxX3B2RjgFuUMygD/RcSGLW3R3JMFG/evoocmoY EpVQ== X-Forwarded-Encrypted: i=1; AJvYcCWIspUKnDP4VsT8tigzmfBv2ndDK4GDw6kCS9sLLS3G8neoT0WLVk6NPhB3b+OzS/YKyKw3kx0eRQ==@vger.kernel.org X-Gm-Message-State: AOJu0Yz2twt/+zNtUSJM1V7ORglu2nFxoXQ4DLLRB5odDDWnDw7RVPws heQMKncwOvfhmr+36sCAv8yLBcaCk+/uu7TO0VKb2w+TrF0kLVjjG+4g9/yzdhPCB5c3bMkI/Lo uBp0ecg== X-Google-Smtp-Source: AGHT+IG4i7fOAFePg97UFWHvr+E2Z6FO0kC5FD9Us3UIujj+wD5TBePM+4bKH0fL2aTTdEKp0RfkKSC8TCCi X-Received: from mizhang-super.c.googlers.com ([34.105.13.176]) (user=mizhang job=sendgmr) by 2002:a25:ba4c:0:b0:e38:10a7:808e with SMTP id 3f1490d57ef6-e38f889f2ddmr1276.0.1732215230445; Thu, 21 Nov 2024 10:53:50 -0800 (PST) Reply-To: Mingwei Zhang Date: Thu, 21 Nov 2024 18:53:11 +0000 In-Reply-To: <20241121185315.3416855-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20241121185315.3416855-1-mizhang@google.com> X-Mailer: git-send-email 2.47.0.371.ga323438b13-goog Message-ID: <20241121185315.3416855-20-mizhang@google.com> Subject: [RFC PATCH 19/22] KVM: x86: Allow host and guest access to IA32_[AM]PERF From: Mingwei Zhang To: Sean Christopherson , Paolo Bonzini , Huang Rui , "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , Viresh Kumar , Srinivas Pandruvada , Len Brown Cc: "H. Peter Anvin" , Perry Yuan , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Jim Mattson , Mingwei Zhang Implement MSR read/write handlers for IA32_APERF and IA32_MPERF to support both host and guest access: - Host userspace access via KVM_[GS]ET_MSRS only reads/writes the snapshot values in vcpu->arch.aperfmperf - Guest writes update both the hardware MSRs (via set_guest_[am]perf) and the snapshots - For host-initiated writes of IA32_MPERF, record the current TSC to establish a new baseline for background cycle accumulation - Guest reads don't reach these handlers as they access the MSRs directly Add both MSRs to msrs_to_save_base[] to ensure they are properly serialized during vCPU state save/restore operations. Signed-off-by: Mingwei Zhang Co-developed-by: Jim Mattson Signed-off-by: Jim Mattson --- arch/x86/kvm/x86.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index cd1f1ae86f83f..4394ecb291401 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -334,6 +334,7 @@ static const u32 msrs_to_save_base[] = { MSR_IA32_UMWAIT_CONTROL, MSR_IA32_XFD, MSR_IA32_XFD_ERR, + MSR_IA32_APERF, MSR_IA32_MPERF, }; static const u32 msrs_to_save_pmu[] = { @@ -4151,6 +4152,26 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) return 1; vcpu->arch.msr_misc_features_enables = data; break; + case MSR_IA32_APERF: + if ((data || !msr_info->host_initiated) && + !guest_can_use(vcpu, X86_FEATURE_APERFMPERF)) + return 1; + + vcpu->arch.aperfmperf.guest_aperf = data; + if (unlikely(!msr_info->host_initiated)) + set_guest_aperf(data); + break; + case MSR_IA32_MPERF: + if ((data || !msr_info->host_initiated) && + !guest_can_use(vcpu, X86_FEATURE_APERFMPERF)) + return 1; + + vcpu->arch.aperfmperf.guest_mperf = data; + if (likely(msr_info->host_initiated)) + vcpu->arch.aperfmperf.host_tsc = rdtsc(); + else + set_guest_mperf(data); + break; #ifdef CONFIG_X86_64 case MSR_IA32_XFD: if (!msr_info->host_initiated && @@ -4524,6 +4545,22 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) msr_info->data = vcpu->arch.guest_fpu.xfd_err; break; #endif + case MSR_IA32_APERF: + /* Guest read access should never reach here. */ + if (!msr_info->host_initiated) + return 1; + + msr_info->data = vcpu->arch.aperfmperf.guest_aperf; + break; + case MSR_IA32_MPERF: + /* Guest read access should never reach here. */ + if (!msr_info->host_initiated) + return 1; + + if (vcpu->arch.mp_state != KVM_MP_STATE_HALTED) + kvm_accumulate_background_guest_mperf(vcpu); + msr_info->data = vcpu->arch.aperfmperf.guest_mperf; + break; default: if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) return kvm_pmu_get_msr(vcpu, msr_info); @@ -7535,6 +7572,11 @@ static void kvm_probe_msr_to_save(u32 msr_index) if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR)) return; break; + case MSR_IA32_APERF: + case MSR_IA32_MPERF: + if (!kvm_cpu_cap_has(KVM_X86_FEATURE_APERFMPERF)) + return; + break; default: break; }