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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 04/15] cpufreq/amd-pstate: Use FIELD_PREP and FIELD_GET macros Date: Thu, 5 Dec 2024 16:28:36 -0600 Message-ID: <20241205222847.7889-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A347:EE_|MW3PR12MB4393:EE_ X-MS-Office365-Filtering-Correlation-Id: 6bc67ce3-af97-4d3c-0930-08dd157c3b59 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: pJdR6pJdB7q58pWvn43EjRGdU2+eorzgFvz4ia1IQ2NlkloY1K65sBCpkJ8+CYO2iTEOl0VNwjTNWt9kFFpFyunv0Hyyaq4n0q0zgOb1/d51ikPJlB2W2xlHTA4HHJtkVGF2avUAX7tfWPu//85UA4qPcMRJNb5+60vlAIjYEXJPVG2vyriIqmuvt0il65UmNvmHc9OAsDhk1NzYF14VpsZehZPQFTp02xzAsnFo+VXwEE58dEbSSRqwLeIgQATH405pNNA42sZ1qQvp3vGjhDjAL/gatwXXHBAwEvmfEU6BnNjKFJsz8wLdLa7XdHllzf8fXfpOs/f8Qhr9Qkn0cJy3b2oQ+2OOu2Fcq9pqFaJTnlXzKI3MnTJ9Pi/BxVByJYXOF2Nql8ZImIjHe5hCxKS5/hUorOBpr/JZOEHMPbVHLBdrwFLoxylbEH4ZV6L7ifVK5FrCdcr+fS2nlvRyeelDNiGbuOLj8rfdo/78zPgh4V8lE2JymRolhnKlHXql6szCMv42sheA6P1FhhJWKcRypgX9otKtB+urWcwHyMVfNtum9weP4IVzCdCJBAUEo39LTSDh0gLg6iywHagdlVcPlI1DwwwmlCyoBzu3dKwlJAkbC0VD7WlINY1X+SdpFhg6OJyDRqeH1Y/LlQZ9HXd2q9iF1UvWkC3Oeg4YRRtIVcw4QQJGK4D/U/u3zncL3LeUBiLnZPAHIsixhvafGfUi4oMKuvFTrGCdqjzEpAKQk1kCU6CSLOeSLt4Xsc0/sIj6s6THkLQLu/JDtiO1/3+Fh1W5X6j69MQFKiq3Lb0FXUJOvOsfAuEYto7FrKkQCkLIxzjUdhvnqw8mvTjgwqnA11G+1SDD2o2HJeQGxlpNzySjge9zncmp/N7pDMfE/1YjCknrpzti20Z5Ru0dLPauQFPyJxog8Lt2YFvt9oAFMnvjfUmLfwS2GFM0e9LEJNnyuu4erv+Medf7v7RX2bZLGaKtn4fmbqmAG93HanULJJSZ+9r2JV38T74QgmOW4dmYt/3/lviYWgiBzJLEDcdBeEyif1wdU+/hjDD9ooefZz97pCagVQez8Sz1Mby/WXkTOD69YYnPLH4qp3/sx+UxJEnS0ml2eTCYXG864Vc98vQpd45aFEKQVW1w8obQ/j340gXYoAJRYmZOzEVJk754Ii7VGUu1EJLqtxJjK5leoW07qNlQ1jenJBJ9R1Dyu4Wmz1/TntvbAuu57Kv66EOFwEYbUrUUNerx8K+BJZa1BLjQnUphWgyYkAmfztMThL3u0lGZFSI+b6Sb/g6VbhhWiU/jP561gwMb06EOwml21t8FuHU3rA+4t1rD+22lrv8onC1pnZNag4nDl9s/mos5TdtILlvJImvxbPzi07k5KeTS1Ykxn+Sx8aBjXHED7kYOED4rLmuBviDXhoBMxGb00EmXNGwcb/Gz6u7uZaZrLOidbTjlpnAewDFJhYxs X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:07.1515 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6bc67ce3-af97-4d3c-0930-08dd157c3b59 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A347.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4393 The FIELD_PREP and FIELD_GET macros improve readability and help to avoid shifting bugs. Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 45 ++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 22e212ca514c5..dbe014f3c2beb 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -22,6 +22,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include @@ -88,6 +89,11 @@ static bool cppc_enabled; static bool amd_pstate_prefcore = true; static struct quirk_entry *quirks; +#define AMD_PSTATE_MAX_PERF_MASK GENMASK(7, 0) +#define AMD_PSTATE_MIN_PERF_MASK GENMASK(15, 8) +#define AMD_PSTATE_DES_PERF_MASK GENMASK(23, 16) +#define AMD_PSTATE_EPP_PERF_MASK GENMASK(31, 24) + /* * AMD Energy Preference Performance (EPP) * The EPP is used in the CCLK DPM controller to drive @@ -182,7 +188,6 @@ static DEFINE_MUTEX(amd_pstate_driver_lock); static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) { - u64 epp; int ret; if (!cppc_req_cached) { @@ -192,9 +197,8 @@ static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) return ret; } } - epp = (cppc_req_cached >> 24) & 0xFF; - return (s16)epp; + return FIELD_GET(AMD_PSTATE_EPP_PERF_MASK, cppc_req_cached); } DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp); @@ -269,12 +273,11 @@ static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) { - int ret; - u64 value = READ_ONCE(cpudata->cppc_req_cached); + int ret; - value &= ~GENMASK_ULL(31, 24); - value |= (u64)epp << 24; + value &= ~AMD_PSTATE_EPP_PERF_MASK; + value |= FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); @@ -533,18 +536,15 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, des_perf = 0; } - value &= ~AMD_CPPC_MIN_PERF(~0L); - value |= AMD_CPPC_MIN_PERF(min_perf); - - value &= ~AMD_CPPC_DES_PERF(~0L); - value |= AMD_CPPC_DES_PERF(des_perf); - /* limit the max perf when core performance boost feature is disabled */ if (!cpudata->boost_supported) max_perf = min_t(unsigned long, nominal_perf, max_perf); - value &= ~AMD_CPPC_MAX_PERF(~0L); - value |= AMD_CPPC_MAX_PERF(max_perf); + value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | + AMD_PSTATE_DES_PERF_MASK); + value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, des_perf); + value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf); if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) { trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq, @@ -1571,16 +1571,11 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) min_perf = min(cpudata->nominal_perf, max_perf); - /* Initial min/max values for CPPC Performance Controls Register */ - value &= ~AMD_CPPC_MIN_PERF(~0L); - value |= AMD_CPPC_MIN_PERF(min_perf); - - value &= ~AMD_CPPC_MAX_PERF(~0L); - value |= AMD_CPPC_MAX_PERF(max_perf); - - /* CPPC EPP feature require to set zero to the desire perf bit */ - value &= ~AMD_CPPC_DES_PERF(~0L); - value |= AMD_CPPC_DES_PERF(0); + value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | + AMD_PSTATE_DES_PERF_MASK); + value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, 0); + value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf); /* Get BIOS pre-defined epp value */ epp = amd_pstate_get_epp(cpudata, value);