@@ -210,10 +210,6 @@ static void early_init_intel(struct cpuinfo_x86 *c)
{
u64 misc_enable;
- if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
- (c->x86 == 0x6 && c->x86_model >= 0x0e))
- set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
-
if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
c->microcode = intel_get_microcode_revision();
@@ -272,6 +268,11 @@ static void early_init_intel(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
}
+ /* Some older CPUs have invariant TSC but may not report it architecturally via 8000_0007 */
+ if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_WILLAMETTE) ||
+ (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE))
+ set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+
/* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
switch (c->x86_vfm) {
case INTEL_ATOM_SALTWELL_MID:
Constant TSC has been architectural on Intel CPUs for a while. Supported CPUs use the architectural Invariant TSC bit in CPUID.80000007. A Family-model check is not required for these CPUs. Prevent unnecessary confusion but restricting the model specific checks to CPUs that need it and moving it closer to the architectural check. Invariant TSC was likely introduced around the Nehalam timeframe on the Xeon side and Saltwell timeframe on the Atom side. Due to interspersed model numbers extend the non-architectural capability setting until Ivybridge to be safe. Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> --- v2: No change. --- arch/x86/kernel/cpu/intel.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)