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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MWH0EPF000989E7.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8632.13 via Frontend Transport; Fri, 11 Apr 2025 08:14:56 +0000 Received: from BLRKPRNAYAK.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 11 Apr 2025 03:14:52 -0500 From: K Prateek Nayak To: "Gautham R. Shenoy" , Mario Limonciello , "Rafael J. Wysocki" , "Viresh Kumar" , , CC: Dhananjay Ugwekar , Huang Rui , Perry Yuan , Meng Li Subject: [PATCH v2] cpufreq/amd-pstate: Enable ITMT support after initializing core rankings Date: Fri, 11 Apr 2025 08:14:39 +0000 Message-ID: <20250411081439.27652-1-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E7:EE_|DS0PR12MB7608:EE_ X-MS-Office365-Filtering-Correlation-Id: e2a74526-e280-45b7-c5ee-08dd78d0f1e2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|82310400026|376014|13003099007; X-Microsoft-Antispam-Message-Info: XDKN/1+NTb0FTwt7ZefFOGTYthPWgmN/Rd/evptzzgt+sHO5v/VyG4zpi1BOjPuAqmk/3AJJc2wPTsoNYsqLI4uWFrL1kVINQjy94H5tLQbdIrje2lZUvv2Rkoqz/TAoH5y5fS8dQZz4wFd1S5NlL3slpTBjK3+HsvDCB0e5ThYXoga4foD0k5wkE6hWsu20yC+KHMZG5zNYUV9CAbUHZQlN5LsTKmuaQP8jR6MAT/wZBZKyhJdeJZJpzuYNFIGnkEIJaG+69o61+h+UgPNVXseFEchKjhEV4mvICplMLy7H3NEOW6f89UpWxTmMAikEQKjwAWkrRPinZcHBDYfDAyQLmqvDc4sqYByDznctecr6eZeA7KfADYwpbXjfLq6fHjheOVzzaOb8dRDIx9Goe5cCC4qz2q2m7g0LEqqnEH7rCs7K6kDF0vZiqcUYIYjZLRS3awM0VjxZGyyF2OueMW/Cdh6uQbvdCikRr7aMF79BC8O5BGpKtdIY8yz42VR5f8IIlexrk4w7N0EbCAeVpEri632H/cQzzizGjV9rSsWDNqBxXaPbstXeEVHQyc6vxXjEDHFmqI5hjFFC9QWvs0opFcdRzv6bEiy3ySzE272lhDMjUAC6SB891ktEPeZ/J43OBHGRRQxjOQWM+KxOvChIp56MIe8wdlZAuyvd2ozemq9t5wtDo92AgETqfDwJmtMEnXCZP3mta5Pm2z8kJXkn1FuRl0uryn84J7FviPvuB1WNlnuDxoKBviIkvARNWizhEdzGzYuyJc1zDN8lo1JnXB8bmZu0laJmOufgZQjlrQ46XylIXHsmRCKnoAO5GwVrmUOHL+CIZ5Pj+T3+C29hSdB5jv8DzCf3LWALh+qAOKHdKy6FeP5BA/EUlNf6iQ3RN2NLWyufnafdWzVVRk1iRs01YEw6B+ItTVtbv/Ai0Z1FUDTC9vBEV+wslWq7RtZ9lyYwi5ScvyWJpHIGMAw+BIPyW60SrvdUVDfSk3N0bMt5dO776ECcNY8dEYTRv6pcljPeaPRxmoDSGk5oS+PSj41fW86V+N4fNUZAVzTNLrG6HEJpChdu0m0uTJrYxJaVVIpFUiFpadHkextmSK4pCJzyHBvCxGAJDyEdIjUHW5wyszPFPphWPiWAH+oRD4yGzaZnKUmhlwhatNJqOWDeb35YDO6UsrZgVi1ubI5GxqAIT+z9oF4/4cELFKaEKoAfjeR9fvSeavw7x0N15Vb407Juz1TVKd7sUtET2t8xRNNVeySo13N3xtph+MZ8yuMN1wXWfkBplD91vysJxDb4v7PNmeRHtC29qX8+dUWFIfKdkqKTJgBaWfrU8Dxo3Iobepn+d0+oBt2mmFNGEhevTv1hLAzxdzST7F30nfq6Sag2atu3bgQUjkcoh0cTlLaSY8nxJpVxhbPTxuJ9pcIpDBNwKqISCzvB/e0FFx5YzAhvnvbEgGXfLTQsNlrBiL5sS33kRlBgdL7XXC2iPMSgHW3FOgSSuZ3wCl8IHOFtM34Y7nB5PgyFs9FxVJk4Zkev7A0ewloaWDwJTTzRSQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(13003099007); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2025 08:14:56.1773 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2a74526-e280-45b7-c5ee-08dd78d0f1e2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7608 When working on dynamic ITMT priority support, it was observed that "asym_prefer_cpu" on AMD systems supporting Preferred Core ranking was always set to the first CPU in the sched group when the system boots up despite another CPU in the group having a higher ITMT ranking. "asym_prefer_cpu" is cached when the sched domain hierarchy is constructed. On AMD systems that support Preferred Core rankings, sched domains are rebuilt when ITMT support is enabled for the first time from amd_pstate*_cpu_init(). Since amd_pstate*_cpu_init() is called to initialize the cpudata for each CPU, the ITMT support is enabled after the first CPU initializes its asym priority but this is too early since other CPUs have not yet initialized their asym priorities and the sched domain is rebuilt only once when the support is toggled on for the first time. Initialize the asym priorities first in amd_pstate*_cpu_init() and then enable ITMT support later in amd_pstate_register_driver() to ensure all CPUs have correctly initialized their asym priorities before sched domain hierarchy is rebuilt. Clear the ITMT support when the amd-pstate driver unregisters since core rankings cannot be trusted unless the update_limits() callback is operational. Remove the delayed work mechanism now that ITMT support is only toggled from the driver init path which is outside the cpuhp critical section. Fixes: f3a052391822 ("cpufreq: amd-pstate: Enable amd-pstate preferred core support") Signed-off-by: K Prateek Nayak --- v1..v2: o Retained the name amd_pstate_init_prefcore() (Mario) o Moved sched_set_itmt_support() towards the end of amd_pstate_register_driver() to address mode switch scenarios. o Disable ITMT support when driver unregisters to prevent incorrect ITMT behavior in absence of update_limits() callback. v1: https://lore.kernel.org/lkml/20250409030004.23008-1-kprateek.nayak@amd.com/ --- drivers/cpufreq/amd-pstate.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) base-commit: 56a49e19e1aea1374e9ba58cfd40260587bb7355 diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index c54c031939c8..b961f3a3b580 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -794,16 +794,6 @@ static void amd_perf_ctl_reset(unsigned int cpu) wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); } -/* - * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks - * due to locking, so queue the work for later. - */ -static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) -{ - sched_set_itmt_support(); -} -static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); - #define CPPC_MAX_PERF U8_MAX static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) @@ -814,14 +804,8 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) cpudata->hw_prefcore = true; - /* - * The priorities can be set regardless of whether or not - * sched_set_itmt_support(true) has been called and it is valid to - * update them at any time after it has been called. - */ + /* Priorities must be initialized before ITMT support can be toggled on. */ sched_set_itmt_core_prio((int)READ_ONCE(cpudata->prefcore_ranking), cpudata->cpu); - - schedule_work(&sched_prefcore_work); } static void amd_pstate_update_limits(unsigned int cpu) @@ -1196,6 +1180,9 @@ static ssize_t show_energy_performance_preference( static void amd_pstate_driver_cleanup(void) { + if (amd_pstate_prefcore) + sched_clear_itmt_support(); + cppc_state = AMD_PSTATE_DISABLE; current_pstate_driver = NULL; } @@ -1238,6 +1225,10 @@ static int amd_pstate_register_driver(int mode) return ret; } + /* Enable ITMT support once all CPUs have initialized their asym priorities. */ + if (amd_pstate_prefcore) + sched_set_itmt_support(); + return 0; }