From patchwork Fri Jul 1 08:20:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 586463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F5CCC433EF for ; Fri, 1 Jul 2022 08:21:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232946AbiGAIVi (ORCPT ); Fri, 1 Jul 2022 04:21:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233958AbiGAIVT (ORCPT ); Fri, 1 Jul 2022 04:21:19 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DED770E78 for ; Fri, 1 Jul 2022 01:21:10 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id q140so1764765pgq.6 for ; Fri, 01 Jul 2022 01:21:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cLvm+NAa5BeE/i7Qo/3zGWdB4t6pSp8QC+y5KpzRMdM=; b=fwnyXMMkk7P3ih5uDwdTYK5Y0ERrPr6v0+GufM5RKzbD6qO14fEsskiV4ITy7/TT1K N8mZFTLF1vS0cVi2PzQHjDsWkiGzMO0mKp4wHVliBpaTHyrIJpcoeaz6IQWtp4ECIrym 4uKpHNYn0heUaULAGTA/TKcBHIH9w4vBpKoBvdjNch4Q5uo9KYKKP7lwcWvyoBBlv67J Fd+GdHfKU2/nFaEebtnD5+BbZLfrHaYyVMeLQlAD7gTJivuaMjHEtp8oFjS0uXiFjRch JQ6i/+xV+EXSO+xkmjlCkexFR8ReX2o6r4NKCvpgSISIdFTXwsDKFqCSWM7K4zYd2vbU kt8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cLvm+NAa5BeE/i7Qo/3zGWdB4t6pSp8QC+y5KpzRMdM=; b=ERNVZYOj8ylodoiK1lkQKuJ79ufv3DRPNWKdo0pR1CxMl7615g5vGAMvrdcZb+sXVU yYjAKLLVJEicQ1f/mxleosqoIx+qRzD7sc2lfvla/Vi1AgJvmIMlGTBYmwpzVslEy0R7 et1BCxYRnV5sGD5l4a/4ngas3Jx3GBl5r4RkVHCfyXjGpRwv2SzeR9v0jbxxLoACW3/t tEaedYKZo3G80hJP62xtDie9xJbQCSxLavOHMASl4hxBICS5EF0sRMx4mavEvgYD+N9o AvWbuXrIb6vkFnYIb9HeS/McLgJ8pZf23uEedXAgMwE2tmOdkK6hZP0N72LsYRRG2pFY 6zZQ== X-Gm-Message-State: AJIora9E4OYcBCUqGvRutkqXkheSxht3lYC01k21zIN8r9dnaO9U8jyE G3JUjfjHTEcJ2eU1fOd2p6ne8ON2C7WGMQ== X-Google-Smtp-Source: AGRyM1s4oLyclufYs9wYwvrJNAdDcdUB4yykbH68vm/CdHwFSxjeFTYOUoGC4sTrKOYQvZyHzhfZlA== X-Received: by 2002:a05:6a00:1312:b0:528:2ed8:7e35 with SMTP id j18-20020a056a00131200b005282ed87e35mr2521119pfu.13.1656663669507; Fri, 01 Jul 2022 01:21:09 -0700 (PDT) Received: from localhost ([122.172.201.58]) by smtp.gmail.com with ESMTPSA id h15-20020a170902680f00b00161e50e2245sm14766175plk.178.2022.07.01.01.21.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Jul 2022 01:21:09 -0700 (PDT) From: Viresh Kumar To: "Rafael J. Wysocki" , Viresh Kumar Cc: linux-pm@vger.kernel.org, Vincent Guittot , Stephen Boyd , Nishanth Menon , linux-kernel@vger.kernel.org Subject: [PATCH V2 09/30] cpufreq: ti: Migrate to dev_pm_opp_set_config() Date: Fri, 1 Jul 2022 13:50:04 +0530 Message-Id: <26dccec60b69c4a6b6902128de25a6b264bc57a4.1656660185.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.31.1.272.g89b43f80a514 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The OPP core now provides a unified API for setting all configuration types, i.e. dev_pm_opp_set_config(). Lets start using it. Signed-off-by: Viresh Kumar --- drivers/cpufreq/ti-cpufreq.c | 38 ++++++++++++++---------------------- 1 file changed, 15 insertions(+), 23 deletions(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 8f9fdd864391..92a873e4d646 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -60,7 +60,6 @@ struct ti_cpufreq_data { struct device_node *opp_node; struct regmap *syscon; const struct ti_cpufreq_soc_data *soc_data; - struct opp_table *opp_table; }; static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data, @@ -324,10 +323,13 @@ static int ti_cpufreq_probe(struct platform_device *pdev) { u32 version[VERSION_COUNT]; const struct of_device_id *match; - struct opp_table *ti_opp_table; struct ti_cpufreq_data *opp_data; const char * const default_reg_names[] = {"vdd", "vbb"}; int ret; + struct dev_pm_opp_config config = { + .supported_hw = version, + .supported_hw_count = ARRAY_SIZE(version), + }; match = dev_get_platdata(&pdev->dev); if (!match) @@ -370,33 +372,23 @@ static int ti_cpufreq_probe(struct platform_device *pdev) if (ret) goto fail_put_node; - ti_opp_table = dev_pm_opp_set_supported_hw(opp_data->cpu_dev, - version, VERSION_COUNT); - if (IS_ERR(ti_opp_table)) { - dev_err(opp_data->cpu_dev, - "Failed to set supported hardware\n"); - ret = PTR_ERR(ti_opp_table); - goto fail_put_node; - } - - opp_data->opp_table = ti_opp_table; - if (opp_data->soc_data->multi_regulator) { - const char * const *reg_names = default_reg_names; + config.regulator_count = ARRAY_SIZE(default_reg_names); if (opp_data->soc_data->reg_names) - reg_names = opp_data->soc_data->reg_names; - ti_opp_table = dev_pm_opp_set_regulators(opp_data->cpu_dev, - reg_names, - ARRAY_SIZE(default_reg_names)); - if (IS_ERR(ti_opp_table)) { - dev_pm_opp_put_supported_hw(opp_data->opp_table); - ret = PTR_ERR(ti_opp_table); - goto fail_put_node; - } + config.regulator_names = opp_data->soc_data->reg_names; + else + config.regulator_names = default_reg_names; + } + + ret = dev_pm_opp_set_config(opp_data->cpu_dev, &config); + if (ret < 0) { + dev_err(opp_data->cpu_dev, "Failed to set OPP config\n"); + goto fail_put_node; } of_node_put(opp_data->opp_node); + register_cpufreq_dt: platform_device_register_simple("cpufreq-dt", -1, NULL, 0);