From patchwork Tue Oct 24 15:17:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Russell King \(Oracle\)" X-Patchwork-Id: 738110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6117C25B6D for ; Tue, 24 Oct 2023 15:19:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343816AbjJXPTU (ORCPT ); Tue, 24 Oct 2023 11:19:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234810AbjJXPSp (ORCPT ); Tue, 24 Oct 2023 11:18:45 -0400 Received: from pandora.armlinux.org.uk (pandora.armlinux.org.uk [IPv6:2001:4d48:ad52:32c8:5054:ff:fe00:142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 242B319AC; Tue, 24 Oct 2023 08:17:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Date:Sender:Message-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Subject:Cc:To:From:References: In-Reply-To:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=dh+jsR2oRY9sfsyFdktS9+0lX1Q0KghWkOaQMlI8IM4=; b=ajV8p/zuaO4aFqKEKamK+Dmcjd D8dgFtK5CysBQTIRIT+StQp57SggyUn6aHwE8gxkjqbOVv2DN7V+g6cCBb29f49yYcE2sSNMAvdlM lBfEOjlCvUAw/SSFrfSvOcE/nkNhteQW47quKJAt3Q2ppKyJhebTCChzAMw1BvjIz/uqr9Me7rc6C OXbLGj8ibVTQmatNPB3Pj0XCQXtsSPFsSR63KTKTYkIvrHYeZfaV06kJmK7coNq0IKdUkZZ9Flhzu FDbmwzv2Tao+LIqjKL5NSNWP/h8P1jDEEMa+HsaduZXnnZ48PYBjuJMF0bkglF5/HJPcoZr36Qlq8 jFJGEFKA==; Received: from e0022681537dd.dyn.armlinux.org.uk ([fd8f:7570:feb6:1:222:68ff:fe15:37dd]:34776 helo=rmk-PC.armlinux.org.uk) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1qvJ9w-0004Q6-3B; Tue, 24 Oct 2023 16:17:33 +0100 Received: from rmk by rmk-PC.armlinux.org.uk with local (Exim 4.94.2) (envelope-from ) id 1qvJ9v-00AqQO-K9; Tue, 24 Oct 2023 16:17:31 +0100 In-Reply-To: References: From: Russell King (Oracle) To: linux-pm@vger.kernel.org, loongarch@lists.linux.dev, linux-acpi@vger.kernel.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, kvmarm@lists.linux.dev, x86@kernel.org, linux-csky@vger.kernel.org, linux-doc@vger.kernel.org, linux-ia64@vger.kernel.org, linux-parisc@vger.kernel.org Cc: Salil Mehta , Jean-Philippe Brucker , jianyong.wu@arm.com, justin.he@arm.com, James Morse , Paul Walmsley , Palmer Dabbelt , Albert Ou Subject: [PATCH 16/39] riscv: Switch over to GENERIC_CPU_DEVICES MIME-Version: 1.0 Content-Disposition: inline Message-Id: Sender: Russell King Date: Tue, 24 Oct 2023 16:17:31 +0100 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: James Morse Now that GENERIC_CPU_DEVICES calls arch_register_cpu(), which can be overridden by the arch code, switch over to this to allow common code to choose when the register_cpu() call is made. This allows topology_init() to be removed. This is an intermediate step to the logic being moved to drivers/acpi, where GENERIC_CPU_DEVICES will do the work when booting with acpi=off. This patch also has the effect of moving the registration of CPUs from subsys to driver core initialisation, prior to any initcalls running. Signed-off-by: James Morse Reviewed-by: Jonathan Cameron Signed-off-by: Russell King (Oracle) --- Changes since RFC v2: * Add note about initialisation order change. --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/setup.c | 19 ++++--------------- 2 files changed, 5 insertions(+), 15 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d607ab0f7c6d..eeb80fb55acc 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -69,6 +69,7 @@ config RISCV select GENERIC_ARCH_TOPOLOGY select GENERIC_ATOMIC64 if !64BIT select GENERIC_CLOCKEVENTS_BROADCAST if SMP + select GENERIC_CPU_DEVICES select GENERIC_EARLY_IOREMAP select GENERIC_ENTRY select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index aac853ae4eb7..311e99741cf8 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -62,7 +62,6 @@ atomic_t hart_lottery __section(".sdata") #endif ; unsigned long boot_cpu_hartid; -static DEFINE_PER_CPU(struct cpu, cpu_devices); /* * Place kernel memory regions on the resource tree so that @@ -307,23 +306,13 @@ void __init setup_arch(char **cmdline_p) riscv_set_dma_cache_alignment(); } -static int __init topology_init(void) +int arch_register_cpu(int cpu) { - int i, ret; + struct cpu *c = &per_cpu(cpu_devices, cpu); - for_each_possible_cpu(i) { - struct cpu *cpu = &per_cpu(cpu_devices, i); - - cpu->hotpluggable = cpu_has_hotplug(i); - ret = register_cpu(cpu, i); - if (unlikely(ret)) - pr_warn("Warning: %s: register_cpu %d failed (%d)\n", - __func__, i, ret); - } - - return 0; + c->hotpluggable = cpu_has_hotplug(cpu); + return register_cpu(c, cpu); } -subsys_initcall(topology_init); void free_initmem(void) {