From patchwork Thu Sep 7 05:21:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 721057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CF29EE14D7 for ; Thu, 7 Sep 2023 05:23:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244207AbjIGFX3 (ORCPT ); Thu, 7 Sep 2023 01:23:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240846AbjIGFX2 (ORCPT ); Thu, 7 Sep 2023 01:23:28 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DE761FC4; Wed, 6 Sep 2023 22:22:55 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38740MbJ021542; Thu, 7 Sep 2023 05:22:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=jtBGwwoG83yHwDO6Ymr3pclpW51kRw6/+vq4etGODyM=; b=R3k9nGTdasxDBW4m1+MlxBs/dJR/TixP/i4PcJpTYIaOsdmbQvNVAfXgaC/KNsyvoIFk 5Id/7F+9iDBwm/5NuGeRBaQqYgShPrVYbWvEFlA6xEsoLLv99fSbkeM+XVNX9ns9IxBA 5IV5m3sqnpOze8rMMlVzP88o7TDnQOffRFjFUPBFxLdtD6wkvPh2A9ZxZ23JzPCSCne+ Kx7q+qvcYB6Mt8YUPklgkwrIShBJ09eb4fYcz7fZHLhbU0ihEjTkBp+OEomflNmrxp4M f4x5fLieho5z88bXpln3GRC38OIFPJhTme9NwtTWbi/UgOwcR6K7uxd170pwggl+d58q sA== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3sy4bqgeby-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Sep 2023 05:22:38 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3875MbSa016947 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 7 Sep 2023 05:22:37 GMT Received: from varda-linux.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Wed, 6 Sep 2023 22:22:32 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v1 07/10] arm64: dts: qcom: ipq5332: populate the opp table based on the eFuse Date: Thu, 7 Sep 2023 10:51:42 +0530 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gmGbyEXOXGgKfaY_-KT0DR1dHsUDO7Uo X-Proofpoint-ORIG-GUID: gmGbyEXOXGgKfaY_-KT0DR1dHsUDO7Uo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-06_12,2023-09-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 malwarescore=0 suspectscore=0 phishscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309070045 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org IPQ53xx have different OPPs available for the CPU based on SoC variant. This can be determined through use of an eFuse register present in the silicon. Add support to read the eFuse and populate the OPPs based on it. Signed-off-by: Kathiravan T Signed-off-by: Varadarajan Narayanan --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 82761ae..3ca3f34 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -91,11 +91,34 @@ }; cpu_opp_table: opp-table-cpu { - compatible = "operating-points-v2"; + compatible = "operating-points-v2-kryo-cpu"; opp-shared; + nvmem-cells = <&cpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + /* + * Listed all supported CPU frequencies and opp-supported-hw + * values to select CPU frequencies based on the limits fused. + * ------------------------------------------------------------ + * Frequency BIT3 BIT2 BIT1 BIT0 opp-supported-hw + * 1.0GHz 1.2GHz 1.5GHz No Limit + * ------------------------------------------------------------ + * 1100000000 1 1 1 1 0xF + * 1500000000 0 0 1 1 0x3 + * ----------------------------------------------------------- + */ + + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0xF>; + clock-latency-ns = <200000>; + }; - opp-1488000000 { - opp-hz = /bits/ 64 <1488000000>; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <950000>; + opp-supported-hw = <0x3>; clock-latency-ns = <200000>; }; }; @@ -150,6 +173,11 @@ reg = <0x000a4000 0x721>; #address-cells = <1>; #size-cells = <1>; + + cpu_speed_bin: cpu_speed_bin@1d { + reg = <0x1d 0x2>; + bits = <7 2>; + }; }; rng: rng@e3000 {