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Peter Anvin" , Peter Zijlstra , Adrian Hunter , Pawan Gupta , Alexander Shishkin , Sumeet Pawnikar , Huang Rui , Tony Luck , Ricardo Neri Subject: [PATCH v3 01/13] x86/msr: Add the MSR definition for AMD CPPC hardware control. Date: Tue, 12 Jul 2022 11:35:36 -0400 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9c19a7a8-4ee3-4ea7-7100-08da641c393c X-MS-TrafficTypeDiagnostic: DM6PR12MB4943:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tJDfLZScNCP9PEsVD3pSS/QPqSGcNRcvtN8TkXpcPW+5xDAnEyEUrsO4Sf+J026Xvliy7JuDX02n5HHQkCTEnCLZXHQ/zcIbVzQnmwXp3LzWLkBw56/EZrU55n5ZpIT2Xh9AetcXYTH+Xee1funXN5cjbgQ+fm6HkqIwYWChXPt/JOkeD+2aAS7M1LyJXhtPclHuxXYZID3on1RU7JoMQJNdYldpjlHX2D77NmNQ/mM8bmGcaFXsckAKcdrDLbztCw+lCHhr66jyxy4OPsSxO/3fLWX9mvi07N+NjmPr8wOLlqafdFx3W8VQfN/3VAtS1xO1x1c7e7KKGqPYXKh1ULnZD6u6cdR1faG4yscnvhghH9Vz5JeRb36G4VXqQRPOKNmOyXnn218JkTfIxYcdDsAOdeApWyT+9So1dg7Lpx3pe1Y8UFsTwwfbsaQ+2heXLrQ95SZWdB2KTtNuIM2oRI1niq3/KIdmCFATVtPKpgLMDDtTN9vinrQU/NvGEIv8MV08EM2kmCote2OsSnLGaZ3ykYhcu0U+D7J7z25dsnpNJSJRNOT/jbs5eG9y7gpp5IljRk3NogIlut1sqwxNz/34leZLlodH7+9G9c+hAyeH2KLzrXe8dfUpYTTg6GBJhbEC3d2UjrKD+yGSytIc53XeiPyO5gIWFkIYNSnIr2JRr9+imk/MOkwHblUyrc5AKFzDll8IUE+j6qEONiY/tUPhAwFMU/jvxzncCT1ZzivZIBe2GRi/H9I1UH+GTvkmybkUSn3pXwn9F0zpKYszQrwdyBfUoXrFbqp3iZLu32cMLfGvasZjKxuh7em+QjTI8Am3Bj452HktKd/UrBgtrx004uG34preEYRWw2/t6D2Kh3E6wwclTLXGbCoqyJw7b8QYLEXqAhVSdN826/aUQwsHYoHZ+BqzDXT3b+8jZ6M= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(136003)(376002)(396003)(346002)(40470700004)(46966006)(36840700001)(356005)(81166007)(40460700003)(40480700001)(6636002)(2616005)(186003)(47076005)(316002)(54906003)(336012)(82310400005)(2906002)(36756003)(110136005)(82740400003)(5660300002)(426003)(4744005)(4326008)(41300700001)(6666004)(26005)(16526019)(8936002)(86362001)(966005)(8676002)(478600001)(70586007)(70206006)(7696005)(36860700001)(7416002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2022 15:36:00.6908 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c19a7a8-4ee3-4ea7-7100-08da641c393c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4943 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This MSR can be used for controlling whether the CPU boost state is enabled in the hardware. AMD Processor Programming Reference (PPR) Link: https://www.amd.com/system/files/TechDocs/40332.pdf [p1095] Link: https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip [p162] Signed-off-by: Perry Yuan --- arch/x86/include/asm/msr-index.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index d27e0581b777..869508de8269 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -548,6 +548,7 @@ #define MSR_AMD_CPPC_CAP2 0xc00102b2 #define MSR_AMD_CPPC_REQ 0xc00102b3 #define MSR_AMD_CPPC_STATUS 0xc00102b4 +#define MSR_AMD_CPPC_HW_CTL 0xc0010015 #define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) #define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)