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[209.132.180.67]) by mx.google.com with ESMTP id u42-v6si1142103pgn.86.2018.08.28.06.39.45; Tue, 28 Aug 2018 06:39:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XDgnm6dP; spf=pass (google.com: best guess record for domain of linux-pm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-pm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728011AbeH1Rb0 (ORCPT + 10 others); Tue, 28 Aug 2018 13:31:26 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:37271 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727094AbeH1Rb0 (ORCPT ); Tue, 28 Aug 2018 13:31:26 -0400 Received: by mail-ed1-f66.google.com with SMTP id b10-v6so1402798eds.4 for ; Tue, 28 Aug 2018 06:39:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=Qc/vEh/hM8XwepQBATbsK+sfjDGVHNzidZ0MvqTnDnY=; b=XDgnm6dPDHNs8LQ0Rb/kna7P+ofp36RdTusFhENVx3KmXTZDD7DP/yn4TQ8hfCyyTA jGWTqm9AqHeO/YJaSE7zOJL44vAO4mTNX/OKccc6WrmrJwVK3ngztkUCpgdqL+4qgh8g Qe9iXug49FuePaXhQY5oHP2vjbF3lmo+Hk5g0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=Qc/vEh/hM8XwepQBATbsK+sfjDGVHNzidZ0MvqTnDnY=; b=PmBrBbZx0G/S7QMs64Aku+n280PE0YCJKDhD+cawR8YpEuwK3jeAkLl934heNnC2x3 CnUUry181Kd8KxudrWvnRgmtATiNSWgYj46Y2K9KhGG0sGMcz6EK52Mei/d5BmSrNWUw 58LfmwVPh0sRbs4LtK0YtWBpbe3JypzI1DO6l0/4Vsooa13raSqfzO9ujEppR8maIWcJ BoEiy98v6iM+2FbpOXkMp5rEVTqNf6zQy2jpTqXvfhBHgiTef4IU4I+AJpImb+4f2i+G iRkC2ch4E4x0QbS1Fu6PsVVDqtleh/o/bbWxwYj1WaNQ5UsTUGuhNVRoF4gzv9BYOSmw YSJw== X-Gm-Message-State: APzg51Cuw2xq9MJ0wlbNH6iuwyWemYKokqkkex7IeaAPX4hCqc2Y2uak RkvfuyIQtxVnt9/r7vtvTI4tTQ== X-Received: by 2002:a50:a959:: with SMTP id m25-v6mr2662021edc.22.1535463582490; Tue, 28 Aug 2018 06:39:42 -0700 (PDT) Received: from localhost ([49.248.200.109]) by smtp.gmail.com with ESMTPSA id i3-v6sm697283eda.84.2018.08.28.06.39.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 28 Aug 2018 06:39:41 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, Zhang Rui , Daniel Lezcano , linux-pm@vger.kernel.org Subject: [PATCH v2 07/11] thermal: tsens: Add the SROT address map Date: Tue, 28 Aug 2018 19:08:36 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On platforms whose device trees specify two address spaces for TSENS, the second one points to the SROT registers. Initialise the SROT map on those platforms. Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke --- drivers/thermal/qcom/tsens-common.c | 14 ++++++++++++-- drivers/thermal/qcom/tsens.h | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) -- 2.17.1 Reviewed-by: Bjorn Andersson diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 0585084630b3..0b8a793f15f4 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -117,16 +117,26 @@ static const struct regmap_config tsens_config = { int __init init_common(struct tsens_device *tmdev) { - void __iomem *tm_base; + void __iomem *tm_base, *srot_base; struct resource *res; struct platform_device *op = of_find_device_by_node(tmdev->dev->of_node); if (!op) return -EINVAL; - /* The driver only uses the TM register address space for now */ if (op->num_resources > 1) { + /* DT with separate SROT and TM address space */ tmdev->tm_offset = 0; + res = platform_get_resource(op, IORESOURCE_MEM, 1); + srot_base = devm_ioremap_resource(&op->dev, res); + if (IS_ERR(srot_base)) + return PTR_ERR(srot_base); + + tmdev->srot_map = devm_regmap_init_mmio(tmdev->dev, + srot_base, &tsens_config); + if (IS_ERR(tmdev->srot_map)) + return PTR_ERR(tmdev->srot_map); + } else { /* old DTs where SROT and TM were in a contiguous 2K block */ tmdev->tm_offset = 0x1000; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 58e98c4d3a8b..b9c4bcf255fa 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -70,6 +70,7 @@ struct tsens_device { struct device *dev; u32 num_sensors; struct regmap *tm_map; + struct regmap *srot_map; u32 tm_offset; struct tsens_context ctx; const struct tsens_ops *ops;