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Thu, 26 Jan 2017 12:38:05 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH v2 0/3] Exynos5433/TM2: add clocks configuration for display subsystem Date: Thu, 26 Jan 2017 13:37:51 +0100 Message-id: <1485434274-6579-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrDIsWRmVeSWpSXmKPExsWy7djPc7pr33ZGGLx+aGaxccZ6VovrX56z Wpw/v4HdYsb5fUwWa4/cZbc4/Kad1YHNY9OqTjaPvi2rGD0+b5ILYI7isklJzcksSy3St0vg ymj6f4Wx4AZvxcrHJ9kbGP9xdTFyckgImEjsPbiPFcIWk7hwbz1bFyMXh5DAUkaJjZtPMEE4 nxklWmYcZ4Pp6Nq/DswWEljGKNGwzRWiqIFJYs7B6cwgCTYBQ4mut11gRSICqhKf2xawgxQx CzxllLi3uIUJJCEsECHRfekEO4jNAlQ0d+oDsDt4Bdwlbu/dwA6xTU7i5LHJUPcdYZNomK3V xcgBZMtKbDrADBF2keiY1w9VLizx6vgWKFtG4vLkbhYIu59RoqlVG8KewShx7i0vhG0tcfj4 RbDxzAJ8EpO2gdwPMp5XoqNNCKLEQ+LC199QvztKPD93mhXi91iJlqULmScwSi9gZFjFKJJa WpybnlpsqlecmFtcmpeul5yfu4kRGIen/x3/uoNx6TGrQ4wCHIxKPLwHdnRECLEmlhVX5h5i lOBgVhLhXfiyM0KINyWxsiq1KD++qDQntfgQozQHi5I4754FV8KFBNITS1KzU1MLUotgskwc nFINjCd+vnzZ//SvlPHDyzPaT1rPn7qu9qju57fVKw6G6ymXFceWsThlWSQba13f13bu4gOV Hzcsi/6b9qt8cmSM+fr78dRjfU5zxLrsj6uwvvwyabJl+PbaM8tmR7oxnLy0/SZTY39lycFu 537FQ0Lhq15+TJ+ldkWRx0nUQXHrwj379k0qudTfukeJpTgj0VCLuag4EQAG8Y8ivwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMLMWRmVeSWpSXmKPExsVy+t/xa7qr3nZGGFxZq26xccZ6VovrX56z Wpw/v4HdYsb5fUwWa4/cZbc4/Kad1YHNY9OqTjaPvi2rGD0+b5ILYI5ys8lITUxJLVJIzUvO T8nMS7dVCg1x07VQUshLzE21VYrQ9Q0JUlIoS8wpBfKMDNCAg3OAe7CSvl2CW0bT/yuMBTd4 K1Y+PsnewPiPq4uRk0NCwESia/86NghbTOLCvfVANheHkMASRolv57uYIJwmJolr2/cxglSx CRhKdL3tAusQEVCV+Ny2gB2kiFngOaPE+939LCAJYYEIie5LJ9hBbBagorlTH7CC2LwC7hK3 925gh1gnJ3Hy2GTWCYzcCxgZVjGKpJYW56bnFhvpFSfmFpfmpesl5+duYgQG4LZjP7fsYOx6 F3yIUYCDUYmHN2NbR4QQa2JZcWXuIUYJDmYlEd6FLzsjhHhTEiurUovy44tKc1KLDzGaAi2f yCwlmpwPjI68knhDE0NzS0MjYwsLcyMjJXHeqR+uhAsJpCeWpGanphakFsH0MXFwSjUw7g2Y +2w1T5VmxY/Th9bzTrWo38UuXzt5X66EhH6z3sNnpQ/tYqSm7f33QHnr1C0Kvi7Pzs91Kv/2 XP/ez3MfhY7rJGfeqMy2dPp+5rj91VKnrsNn+Zk7xavnzzrItuDyj1oLnd2us2UX/9q64JOZ oOivHZ3CVzbPOq4qItn12f7Lm9Ozb59SfqXEUpyRaKjFXFScCABrDHztVgIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170126123805eucas1p23881b01fa3f9719e2bfea9cd5cf1b429 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170126123805eucas1p23881b01fa3f9719e2bfea9cd5cf1b429 X-RootMTR: 20170126123805eucas1p23881b01fa3f9719e2bfea9cd5cf1b429 References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Hello, This patchset is a next step to add support for all power domains on Exynos5433 SoCs. This patchset contains patches for initial clocks configuration on TM2/TM2e boards. Till now display subsystem worked only because the clock hierarchy has been configured by the bootloader. However when power domains are added, such configuration might be lost if the display power domain get turned off before display clock controller's probe. Patches have been generated on top of linux-next from 25th January 2017. This is a part of a larger task, which goal is to add support for power domains on Exynos5433 SoCs and TM2/TM2e boards. All patches needed to get it working have been pushed to the following git repo: https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd Best regards Marek Szyprowski Samsung R&D Institute Poland Changelog: v2: - corrected DISP PLL rate from 266MHz to 250MHz (TM2) and 278MHz (TM2e) - added a patch with PLL data for 250MHZ and 278MHz rates v1: - initial version Patch summary: Marek Szyprowski (3): clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 --------- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 29 ++++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 29 ++++++++++++++++++++++ drivers/clk/samsung/clk-exynos5433.c | 8 ++++-- include/dt-bindings/clock/exynos5433.h | 5 +++- 5 files changed, 68 insertions(+), 15 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html