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Tue, 20 Aug 2024 09:15:04 +0000 (GMT) Received: from epsmgmc1p1new.samsung.com (unknown [182.195.42.40]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20240820091504epsmtrp1361a1f5dc3c860bb8a045fb3b1b623cd~tZQT9Y0Fm2606226062epsmtrp11; Tue, 20 Aug 2024 09:15:04 +0000 (GMT) X-AuditID: b6c32a43-a0fff700000022c5-ee-66c45e984513 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmc1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 59.7F.07567.89E54C66; Tue, 20 Aug 2024 18:15:04 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.60]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20240820091504epsmtip1768782e35c659e603dd865e7177d4a83~tZQTyTqtp3093730937epsmtip1T; Tue, 20 Aug 2024 09:15:04 +0000 (GMT) From: Sunyeal Hong To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sunyeal Hong Subject: [PATCH v8 0/4] initial clock support for exynosauto v920 SoC Date: Tue, 20 Aug 2024 18:14:56 +0900 Message-ID: <20240820091501.3395841-1-sunyeal.hong@samsung.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPJsWRmVeSWpSXmKPExsWy7bCmqe6MuCNpBmsfGFk8mLeNzWLN3nNM Fte/PGe1mH/kHKvF+fMb2C02Pb7GavGx5x6rxeVdc9gsZpzfx2Rx8ZSrxf89O9gtDr9pZ7X4 d20ji0XTsvVMDnwe72+0sntsWtXJ5rF5Sb1H35ZVjB6fN8kFsEZl22SkJqakFimk5iXnp2Tm pdsqeQfHO8ebmhkY6hpaWpgrKeQl5qbaKrn4BOi6ZeYA3amkUJaYUwoUCkgsLlbSt7Mpyi8t SVXIyC8usVVKLUjJKTAv0CtOzC0uzUvXy0stsTI0MDAyBSpMyM7o3biFseA9f8WzKw4NjBt5 uhg5OSQETCRW3ZvG3MXIxSEksINR4mzTSnYI5xOjxPJrX6Ey3xgl+ne/Y4FpubZhLiuILSSw l1Fi1hRtiKKPjBJn5r1n6mLk4GAT0JX4888BJC4isIdJYsv5JUwgDrPAWUaJu3MWsIN0Cwu4 Slw+so4ZxGYRUJXo+rSWEcTmFbCXOHqyhxlim7zExTXP2SDighInZz4Bu4IZKN68dTbYeRIC rRwSh65dBNssIeAicfk2K0SvsMSr41vYIWwpiZf9bVB2vsTk62+ZIHobGCWu/euGWmYvsejM T3aQOcwCmhLrd+lDjFSWOHILai2fRMfhv+wQYV6JjjYhiEY1iU9XLkMNkZE4duIZlO0hMevw RGhYxUpsaLzDMoFRfhaSZ2YheWYWwt4FjMyrGMVSC4pz01OTjQoM4XGanJ+7iRGcUrWcdzBe mf9P7xAjEwfjIUYJDmYlEd7ulwfThHhTEiurUovy44tKc1KLDzGaAoN3IrOUaHI+MKnnlcQb mlgamJiZGZobmRqYK4nz3mudmyIkkJ5YkpqdmlqQWgTTx8TBKdXAtMnBmeNPZfXrXl27zQwt ly9WBIjYJK/XnNjQYJPs1nJw4cV9u9vUnp/gmPxC0jjh5iy1vJe/TqXsMr92dO2N+wEtBfsd DvJJTw0qWHNLolG5dvfibSIXlrGotT3vEsxL/xz+jv9OR1AaR71qukrwjEWG5h43Q/Je6nyJ 6z64w89T9G4b11OGmivlvx8wXf3Z1Gi3dkdv1rSKKzefxj6bMje4+J8jD2Pq9TMh95bwmy/2 M7uYycv+f17o2dunykLfXPJYyWSuULxgq9O+k4udDJYGxV2r6i34mfjmacoKk/lxO26VMP1R Yo1VYxZtk1386NfhKMOLTN0OrCu2P+k55mlw/omD0LW5fjNs/pYaKLEUZyQaajEXFScCADFO z4YyBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrPLMWRmVeSWpSXmKPExsWy7bCSnO6MuCNpBtd+iFs8mLeNzWLN3nNM Fte/PGe1mH/kHKvF+fMb2C02Pb7GavGx5x6rxeVdc9gsZpzfx2Rx8ZSrxf89O9gtDr9pZ7X4 d20ji0XTsvVMDnwe72+0sntsWtXJ5rF5Sb1H35ZVjB6fN8kFsEZx2aSk5mSWpRbp2yVwZfRu 3MJY8J6/4tkVhwbGjTxdjJwcEgImEtc2zGUFsYUEdjNKvF/GBhGXkdjY8J8dwhaWuN9yBKiG C6jmPaPE7L47zF2MHBxsAroSf/45gMRFBA4xSUz8/JQFxGEWuMwocezuZGaQbmEBV4nLR9aB 2SwCqhJdn9Yygti8AvYSR0/2MENskJe4uOY5G0RcUOLkzCcsIDYzULx562zmCYx8s5CkZiFJ LWBkWsUomVpQnJuem2xYYJiXWq5XnJhbXJqXrpecn7uJERzmWho7GO/N/6d3iJGJg/EQowQH s5IIb/fLg2lCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeQ1nzE4REkhPLEnNTk0tSC2CyTJxcEo1 MCXLi08TLTQIkptYd199S/3/u6cdtjpVLgzcpP1pzbV7H3rMGC6XWvnfVb05/e3zbT39Ju9O yW4QCbSzdBAzXHAq6Jam/gLhyW6ZPeubT9l7z/V+wqc2tVf/v0SvbIvOJn4/tr1LEl6wTVpY u2lD2Eu/n9EHvwlve/Zg86I6ptJ1Yo6+szfZTCleP2dV/60koekpjJvqlNkWPPnInHvVp3XS 89/bS0/lnKxle3NRrS/7yZLVp97tWXv2tv2RngXvqr4Jnz2c4vZOn/ch8+dzR99cTlq7ntPc IsfpcYTqeV1FqXKv4EU5j7O2zvvNM9HjcsG7vIrFuiITlMT2Bcf9WnJVnvl0RoHdhIqeAIN3 NbuVWIozEg21mIuKEwEcRHiF4gIAAA== X-CMS-MailID: 20240820091504epcas2p4b492128d21e5f12cdc084995059c6502 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240820091504epcas2p4b492128d21e5f12cdc084995059c6502 References: This patchset adds initial clock driver support for Exynos Auto v920 SoC. This driver uses HW Auto Clock gating. So all gate clocks did not register. Below CMU blocks are supported in this patchset and remains will be implemented later. - CMU_TOP - CMU_PERIC0/1 - CMU_MISC - CMU_HSI0/1 Changes in v8: - Resend it because v7 includes other SoC patches Changes in v7: - Combine duplicate clock description Changes in v6: - Add peric1, mis and hsi0/1 in the bindings document Changes in v5: - Change CMU_TOP odd numbering - Move the descriptions and names common clocks properties Changes in v4: - Change PLL_531x fdiv type and mask bit - Change PLL_531x mdiv type Changes in v3: - Change SoC name from Exynos Auto to ExynosAuto - Change the makefile order to the bottom of exynosautov9 - Add PLL_531x formula for integer PLL Changes in v2: - Fix typo from v209 to v920 - Change USI clock to appropriate - Merge headers into binding patches - Change clock-name to the recommended name Sunyeal Hong (4): dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings arm64: dts: exynos: add initial CMU clock nodes in ExynosAuto v920 clk: samsung: clk-pll: Add support for pll_531x clk: samsung: add top clock support for ExynosAuto v920 SoC .../clock/samsung,exynosautov920-clock.yaml | 162 +++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 40 +- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynosautov920.c | 1173 +++++++++++++++++ drivers/clk/samsung/clk-pll.c | 44 + drivers/clk/samsung/clk-pll.h | 1 + .../clock/samsung,exynosautov920.h | 191 +++ 7 files changed, 1599 insertions(+), 13 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml create mode 100644 drivers/clk/samsung/clk-exynosautov920.c create mode 100644 include/dt-bindings/clock/samsung,exynosautov920.h