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[v9,0/4] initial clock support for exynosauto v920 SoC

Message ID 20240821232652.1077701-1-sunyeal.hong@samsung.com
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Series initial clock support for exynosauto v920 SoC | expand

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Sunyeal Hong Aug. 21, 2024, 11:26 p.m. UTC 
This patchset adds initial clock driver support for Exynos Auto v920 SoC.
This driver uses HW Auto Clock gating. So all gate clocks did not register.

Below CMU blocks are supported in this patchset and remains will be implemented later.

- CMU_TOP
- CMU_PERIC0/1
- CMU_MISC
- CMU_HSI0/1

Changes in v9:
 - Modify the parent clock name of peric0_cmu to match the device tree

Changes in v8:
 - Resend it because v7 includes other SoC patches

Changes in v7:
 - Combine duplicate clock description

Changes in v6:
 - Add peric1, mis and hsi0/1 in the bindings document

Changes in v5:
 - Change CMU_TOP odd numbering
 - Move the descriptions and names common clocks properties

Changes in v4:
 - Change PLL_531x fdiv type and mask bit
 - Change PLL_531x mdiv type

Changes in v3:
 - Change SoC name from Exynos Auto to ExynosAuto
 - Change the makefile order to the bottom of exynosautov9
 - Add PLL_531x formula for integer PLL

Changes in v2:
 - Fix typo from v209 to v920
 - Change USI clock to appropriate
 - Merge headers into binding patches
 - Change clock-name to the recommended name

Sunyeal Hong (4):
  dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings
  arm64: dts: exynos: add initial CMU clock nodes in ExynosAuto v920
  clk: samsung: clk-pll: Add support for pll_531x
  clk: samsung: add top clock support for ExynosAuto v920 SoC

 .../clock/samsung,exynosautov920-clock.yaml   |  162 +++
 .../arm64/boot/dts/exynos/exynosautov920.dtsi |   40 +-
 drivers/clk/samsung/Makefile                  |    1 +
 drivers/clk/samsung/clk-exynosautov920.c      | 1173 +++++++++++++++++
 drivers/clk/samsung/clk-pll.c                 |   44 +
 drivers/clk/samsung/clk-pll.h                 |    1 +
 .../clock/samsung,exynosautov920.h            |  191 +++
 7 files changed, 1599 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
 create mode 100644 drivers/clk/samsung/clk-exynosautov920.c
 create mode 100644 include/dt-bindings/clock/samsung,exynosautov920.h

Comments

Krzysztof Kozlowski Aug. 23, 2024, 7:42 a.m. UTC | #1 
On Thu, 22 Aug 2024 08:26:49 +0900, Sunyeal Hong wrote:
> Add dt-schema for ExynosAuto v920 SoC clock controller.
> Add device tree clock binding definitions for below CMU blocks.
> 
> - CMU_TOP
> - CMU_PERIC0/1
> - CMU_MISC
> - CMU_HSI0/1
> 
> [...]

Applied, thanks!

[1/4] dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings
      https://git.kernel.org/krzk/linux/c/997daa8de64ccbb4dc68d250510893597d485de4

Best regards,
Krzysztof Kozlowski Aug. 23, 2024, 7:42 a.m. UTC | #2 
On Thu, 22 Aug 2024 08:26:51 +0900, Sunyeal Hong wrote:
> pll531x PLL is used in Exynos Auto v920 SoC for shared pll.
> pll531x: Integer/fractional PLL with mid frequency FVCO (800 to 3120 MHz)
> 
> PLL531x
> FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL
> FOUT = (MDIV + F/2^32-F[31]) x FIN/(PDIV x 2^SDIV) for fractional PLL
> 
> [...]

Applied, thanks!

[3/4] clk: samsung: clk-pll: Add support for pll_531x
      https://git.kernel.org/krzk/linux/c/9224e288f2e1f9161cf0c54122ac9168b6b68877

Best regards,