[v2,0/4] Fix CPUCL0 add CPUCL1/2 clock support for exynosauto v920 SoC

Message ID	20250428113517.426987-1-shin.son@samsung.com
Headers	show Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EA7625E800 for <linux-samsung-soc@vger.kernel.org>; Mon, 28 Apr 2025 11:35:43 +0000 (UTC) From: Shin Son <shin.son@samsung.com> To: Krzysztof Kozlowski <krzk@kernel.org>, Sylwester Nawrocki <s.nawrocki@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Alim Akhtar <alim.akhtar@samsung.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Sunyeal Hong <sunyeal.hong@samsung.com> Cc: Shin Son <shin.son@samsung.com>, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/4] Fix CPUCL0 add CPUCL1/2 clock support for exynosauto v920 SoC Date: Mon, 28 Apr 2025 20:35:13 +0900 Message-ID: <20250428113517.426987-1-shin.son@samsung.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y References: <CGME20250428113540epcas2p4f8a2d6b473bdf6d71bd598e71fbf70c9@epcas2p4.samsung.com>
Series	Fix CPUCL0 add CPUCL1/2 clock support for exynosauto v920 SoC \| expand [v2,0/4] Fix CPUCL0 add CPUCL1/2 clock support for exynosauto v920 SoC [v2,1/4] dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions [v2,2/4] clk: samsung: exynosautov920: add cpucl1/2 clock support [v2,3/4] clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition [v2,4/4] arm64: dts: exynosautov920: add cpucl1/2 clock DT nodes

Message ID

20250428113517.426987-1-shin.son@samsung.com

Headers

From: Shin Son <shin.son@samsung.com>
To: Krzysztof Kozlowski <krzk@kernel.org>, Sylwester Nawrocki
	<s.nawrocki@samsung.com>, Chanwoo Choi <cw00.choi@samsung.com>, Alim Akhtar
	<alim.akhtar@samsung.com>, Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, Conor Dooley
	<conor+dt@kernel.org>, Sunyeal Hong <sunyeal.hong@samsung.com>
Cc: Shin Son <shin.son@samsung.com>, linux-samsung-soc@vger.kernel.org,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 0/4] Fix CPUCL0 add CPUCL1/2 clock support for exynosauto
 v920 SoC
Date: Mon, 28 Apr 2025 20:35:13 +0900
Message-ID: <20250428113517.426987-1-shin.son@samsung.com>
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 <CGME20250428113540epcas2p4f8a2d6b473bdf6d71bd598e71fbf70c9@epcas2p4.samsung.com>

Series

Fix CPUCL0 add CPUCL1/2 clock support for exynosauto v920 SoC | expand

Message

손신 April 28, 2025, 11:35 a.m. UTC

This patchset fixes the incorrect CLKS_NR_CPUCL0 definition and
adds the CMU_CPUCL1 and CMU_CPUCL2 block to support exynosauto v920 SoC.

Changes in v2:
- Separate the fix into its own patch
- Remove the extra blank line

Shin Son (4):
  dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions
  clk: samsung: exynosautov920: add cpucl1/2 clock support
  clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition
  arm64: dts: exynosautov920: add cpucl1/2 clock DT nodes

 .../clock/samsung,exynosautov920-clock.yaml   |  44 ++++
 .../arm64/boot/dts/exynos/exynosautov920.dtsi |  26 +++
 drivers/clk/samsung/clk-exynosautov920.c      | 208 +++++++++++++++++-
 .../clock/samsung,exynosautov920.h            |  32 +++
 4 files changed, 309 insertions(+), 1 deletion(-)