From patchwork Sat Nov 12 05:01:48 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inderpal Singh X-Patchwork-Id: 5080 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D4A9C23EF6 for ; Sat, 12 Nov 2011 05:00:31 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id C13DAA18AC3 for ; Sat, 12 Nov 2011 05:00:31 +0000 (UTC) Received: by faan26 with SMTP id n26so6493011faa.11 for ; Fri, 11 Nov 2011 21:00:31 -0800 (PST) Received: by 10.152.105.226 with SMTP id gp2mr8342052lab.28.1321074031467; Fri, 11 Nov 2011 21:00:31 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.40.7 with SMTP id t7cs75562lak; Fri, 11 Nov 2011 21:00:31 -0800 (PST) Received: by 10.236.86.237 with SMTP id w73mr1224497yhe.46.1321074028695; Fri, 11 Nov 2011 21:00:28 -0800 (PST) Received: from mail-gx0-f178.google.com (mail-gx0-f178.google.com [209.85.161.178]) by mx.google.com with ESMTPS id e6si1567994yba.20.2011.11.11.21.00.27 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 11 Nov 2011 21:00:28 -0800 (PST) Received-SPF: neutral (google.com: 209.85.161.178 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) client-ip=209.85.161.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.161.178 is neither permitted nor denied by best guess record for domain of inderpal.singh@linaro.org) smtp.mail=inderpal.singh@linaro.org Received: by ggnk5 with SMTP id k5so875456ggn.37 for ; Fri, 11 Nov 2011 21:00:27 -0800 (PST) Received: by 10.68.4.38 with SMTP id h6mr23331239pbh.5.1321074027075; Fri, 11 Nov 2011 21:00:27 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id f1sm27624004pba.7.2011.11.11.21.00.24 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 11 Nov 2011 21:00:26 -0800 (PST) From: Inderpal Singh To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, patches@linaro.org, Inderpal Singh Subject: [PATCH] ARM: SAMSUNG: Save/restore GPIO drive strength across suspend/resume Date: Sat, 12 Nov 2011 10:31:48 +0530 Message-Id: <1321074108-10025-1-git-send-email-inderpal.singh@linaro.org> X-Mailer: git-send-email 1.7.1 GPIO driver strength settings are not preserved across suspend/resume for s5pc100, s5pv210 and Exynos platforms which has been the cause of mmc/sd card read/write failures after resume. Fix this by saving and restoring the GPIO driver strength register settings across suspend/resume. Signed-off-by: Inderpal Singh --- 1. This change is applicable only for s5pc100, s5pv210 and Exynos platforms. For all other platforms, the driver strength registers are part of special port configuration register (SPCON) and these registers are saved and restored separately from the GPIO bank registers. For s5pc100, s5pv210 and Exynos platforms, the driver strength values are saved along with the GPIO bank registers. 2. An additional entry is added to the 'pm_save' array of 'struct samsung_gpio_chip' for saving driver strength values. 3. Tested with v210 and v310 smdk boards arch/arm/plat-samsung/include/plat/gpio-core.h | 2 +- arch/arm/plat-samsung/pm-gpio.c | 13 +++++++++++-- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 1fe6917..8871b4c 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -69,7 +69,7 @@ struct samsung_gpio_chip { int group; spinlock_t lock; #ifdef CONFIG_PM - u32 pm_save[4]; + u32 pm_save[5]; #endif }; diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index 4be016e..5493f38 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -21,12 +21,14 @@ #include #include +#include /* PM GPIO helpers */ #define OFFS_CON (0x00) #define OFFS_DAT (0x04) #define OFFS_UP (0x08) +#define OFFS_DRV_STRGTH (0x0C) static void samsung_gpio_pm_1bit_save(struct samsung_gpio_chip *chip) { @@ -199,6 +201,9 @@ static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip) chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP); + if (soc_is_s5pc100() || soc_is_s5pv210() || soc_is_exynos4210()) + chip->pm_save[4] = __raw_readl(chip->base + OFFS_DRV_STRGTH); + if (chip->chip.ngpio > 8) chip->pm_save[0] = __raw_readl(chip->base - 4); } @@ -285,6 +290,9 @@ static void samsung_gpio_pm_4bit_resume(struct samsung_gpio_chip *chip) __raw_writel(chip->pm_save[2], base + OFFS_DAT); __raw_writel(chip->pm_save[3], base + OFFS_UP); + if (soc_is_s5pc100() || soc_is_s5pv210() || soc_is_exynos4210()) + __raw_writel(chip->pm_save[4], base + OFFS_DRV_STRGTH); + if (chip->chip.ngpio > 8) { S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n", chip->chip.label, old_gpcon[0], old_gpcon[1], @@ -338,12 +346,13 @@ void samsung_pm_save_gpios(void) samsung_pm_save_gpio(ourchip); - S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n", + S3C_PMDBG("%s: save %08x,%08x,%08x,%08x,%08x\n", ourchip->chip.label, ourchip->pm_save[0], ourchip->pm_save[1], ourchip->pm_save[2], - ourchip->pm_save[3]); + ourchip->pm_save[3], + ourchip->pm_save[4]); gpio_nr += ourchip->chip.ngpio; gpio_nr += CONFIG_S3C_GPIO_SPACE;