From patchwork Tue May 22 09:05:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 8855 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 95C1023F0A for ; Tue, 22 May 2012 09:15:58 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 48B15A186B8 for ; Tue, 22 May 2012 09:15:58 +0000 (UTC) Received: by yhpp61 with SMTP id p61so6340180yhp.11 for ; Tue, 22 May 2012 02:15:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=AmpO2BI8ipf5t+G81PkoUZ3abb9bEnyrrEr4NYabxP4=; b=pRM59jzJvfY9oZ3rw25BFCrW8Q5c/DSc4t17VjJe+vPqSlFDgLdi1h0S+mzkitUCKK saKP+us6lcveG3v5N4C5qWyigUOEvXSwm14j7lbhUac9vB8CFGARNaAdycr6ajtHckXZ m0gYeZQuuDvXgT48vrUYE7XCV7MJ3DtGkcJXwZm3fONbkILzIFo5bRVdXZuk9ML0V3iG vYz4Jz+hX6seYhUXiNKOez83wFvR41ghATPKW6XTD9Othe4cEUs0nZm3Z2FPacZMs6zw 223q+Kic5vHX9WF8e59AUjqvuRzik3fZFqr11MdYwjiumLRb6Fl3Jkku/StPukaO8FWQ i+0g== Received: by 10.42.89.72 with SMTP id f8mr14380532icm.33.1337678157180; Tue, 22 May 2012 02:15:57 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp350927ibd; Tue, 22 May 2012 02:15:56 -0700 (PDT) Received: by 10.68.228.170 with SMTP id sj10mr9942260pbc.106.1337678156294; Tue, 22 May 2012 02:15:56 -0700 (PDT) Received: from mail-pz0-f50.google.com (mail-pz0-f50.google.com [209.85.210.50]) by mx.google.com with ESMTPS id rq4si2003764pbc.89.2012.05.22.02.15.56 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 May 2012 02:15:56 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) client-ip=209.85.210.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) smtp.mail=sachin.kamat@linaro.org Received: by danh15 with SMTP id h15so9541304dan.37 for ; Tue, 22 May 2012 02:15:55 -0700 (PDT) Received: by 10.68.129.72 with SMTP id nu8mr20756147pbb.56.1337678155859; Tue, 22 May 2012 02:15:55 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id py5sm26107566pbb.1.2012.05.22.02.15.53 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 22 May 2012 02:15:55 -0700 (PDT) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, sachin.kamat@linaro.org, patches@linaro.org Subject: [PATCH 1/2] ARM: EXYNOS: Update HSOTG PHY clock setting for Exynos4x12 Date: Tue, 22 May 2012 14:35:28 +0530 Message-Id: <1337677529-7325-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.4.1 X-Gm-Message-State: ALoCoQkoQGnoW0MelI/Ff7bq09fXf6DZNztzOIOAOt7TI3nNvvfHGJHfbhWM6x6s6ug1IOMtC3oB Adds clock setting entries for Exynos4212 and Exynos4412 platforms. Signed-off-by: Sachin Kamat --- Based on Kukjin Kim's v3.5-for-usb-2 branch. --- arch/arm/mach-exynos/include/mach/regs-usb-phy.h | 5 ++ arch/arm/mach-exynos/setup-usb-phy.c | 47 ++++++++++++++++----- arch/arm/plat-samsung/include/plat/cpu.h | 4 ++ 3 files changed, 45 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h index c337cf3..bab28d9 100644 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h @@ -38,8 +38,13 @@ #define CLKSEL_MASK (0x3 << 0) #define CLKSEL_SHIFT (0) #define CLKSEL_48M (0x0 << 0) +#define CLKSEL_9600K (0x0 << 0) +#define CLKSEL_10M (0x1 << 0) #define CLKSEL_12M (0x2 << 0) +#define CLKSEL_19200K (0x3 << 0) #define CLKSEL_24M (0x3 << 0) +#define CLKSEL_20M (0x4 << 0) +#define EXYNOS4X12_CLKSEL_24M (0x5 << 0) #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c index 1af0a7f..b8cf0f8 100644 --- a/arch/arm/mach-exynos/setup-usb-phy.c +++ b/arch/arm/mach-exynos/setup-usb-phy.c @@ -36,17 +36,42 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev) xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { - switch (clk_get_rate(xusbxti_clk)) { - case 12 * MHZ: - phyclk |= CLKSEL_12M; - break; - case 24 * MHZ: - phyclk |= CLKSEL_24M; - break; - default: - case 48 * MHZ: - /* default reference clock */ - break; + if (soc_is_exynos4210()) { + switch (clk_get_rate(xusbxti_clk)) { + case 12 * MHZ: + phyclk |= CLKSEL_12M; + break; + case 24 * MHZ: + phyclk |= CLKSEL_24M; + break; + default: + case 48 * MHZ: + /* default reference clock */ + break; + } + } else if (soc_is_exynos4212() || soc_is_exynos4412()) { + switch (clk_get_rate(xusbxti_clk)) { + case 9600 * KHZ: + phyclk |= CLKSEL_9600K; + break; + case 10 * MHZ: + phyclk |= CLKSEL_10M; + break; + case 12 * MHZ: + phyclk |= CLKSEL_12M; + break; + case 19200 * KHZ: + phyclk |= CLKSEL_19200K; + break; + case 20 * MHZ: + phyclk |= CLKSEL_20M; + break; + default: + case 24 * MHZ: + /* default reference clock */ + phyclk |= EXYNOS4X12_CLKSEL_24M; + break; + } } clk_put(xusbxti_clk); } diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 787ceac..6a6ff7e 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } +#ifndef KHZ +#define KHZ (1000) +#endif + #ifndef MHZ #define MHZ (1000*1000) #endif