From patchwork Fri Apr 19 06:16:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 16255 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-fa0-f72.google.com (mail-fa0-f72.google.com [209.85.161.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id C959323A42 for ; Fri, 19 Apr 2013 06:29:13 +0000 (UTC) Received: by mail-fa0-f72.google.com with SMTP id t1sf5274186fae.11 for ; Thu, 18 Apr 2013 23:28:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:mime-version:x-beenthere:x-received:received-spf :x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=dIlTfTtSSlG4gV6aTSHciqlcMKhAhZWKwCi6VhXrCI8=; b=iFKOd8QSKHseFiZzI2fQSs+fKKMUotcbg1m+t3btCmWXLSAnYplbw/TFHBh8ICcxEO S1eN6Rp4CdJq0YLlxnDtcQ3Ez8w0FbnJ/f/pfeWyQEsRyclkhdiPCUrl4FlmysYxjfs0 bavyoubjwawtI/n8rgnfG5ZM/Li9ijdWNo2jvwAU6OkNvHWUtIS8/PneuENlsYUqr4wD UZOaMyZD92yI5MjNcdnZ5kjlv2XCLttJegW1GFO2aOJQkUnrEvLJSt/LhS5JlpFNN05o mft3nysb486RlcxCmnd6lXAhug3z/wNLZMf2IZ6korbhP9S5kyfkxpLsYKnwXhlw1fT8 Rd8Q== X-Received: by 10.112.59.10 with SMTP id v10mr2796815lbq.12.1366352913993; Thu, 18 Apr 2013 23:28:33 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.20.170 with SMTP id o10ls167106lae.31.gmail; Thu, 18 Apr 2013 23:28:33 -0700 (PDT) X-Received: by 10.112.61.6 with SMTP id l6mr7279576lbr.57.1366352913635; Thu, 18 Apr 2013 23:28:33 -0700 (PDT) Received: from mail-la0-x235.google.com (mail-la0-x235.google.com [2a00:1450:4010:c03::235]) by mx.google.com with ESMTPS id rm1si4761845lbb.110.2013.04.18.23.28.33 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Apr 2013 23:28:33 -0700 (PDT) Received-SPF: neutral (google.com: 2a00:1450:4010:c03::235 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=2a00:1450:4010:c03::235; Received: by mail-la0-f53.google.com with SMTP id fp13so3246520lab.40 for ; Thu, 18 Apr 2013 23:28:33 -0700 (PDT) X-Received: by 10.152.20.74 with SMTP id l10mr7323507lae.40.1366352913410; Thu, 18 Apr 2013 23:28:33 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.112.79.101 with SMTP id i5csp192445lbx; Thu, 18 Apr 2013 23:28:32 -0700 (PDT) X-Received: by 10.68.93.1 with SMTP id cq1mr17524769pbb.50.1366352911137; Thu, 18 Apr 2013 23:28:31 -0700 (PDT) Received: from mail-pd0-f175.google.com (mail-pd0-f175.google.com [209.85.192.175]) by mx.google.com with ESMTPS id rr3si11183585pbc.92.2013.04.18.23.28.30 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Apr 2013 23:28:31 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.192.175 is neither permitted nor denied by best guess record for domain of sachin.kamat@linaro.org) client-ip=209.85.192.175; Received: by mail-pd0-f175.google.com with SMTP id g10so2025485pdj.6 for ; Thu, 18 Apr 2013 23:28:30 -0700 (PDT) X-Received: by 10.68.220.106 with SMTP id pv10mr17367227pbc.52.1366352910154; Thu, 18 Apr 2013 23:28:30 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPS id gi10sm12276038pbc.40.2013.04.18.23.28.27 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 18 Apr 2013 23:28:29 -0700 (PDT) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, sachin.kamat@linaro.org, patches@linaro.org, Thomas Abraham , Mike Turquette Subject: [PATCH 1/1] clk: exynos4: Add clock entries for TMU Date: Fri, 19 Apr 2013 11:46:06 +0530 Message-Id: <1366352166-20967-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQn7ivWr7IgV7Uj8qO0XQAZTUJGCA99x5WKcr2G6S8Mo4B7TFFTq3hXy/kGFEle7n0Vl0WLs X-Original-Sender: sachin.kamat@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2a00:1450:4010:c03::235 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Added clock entries for thermal management unit (TMU) for Exynos4 SoCs. Signed-off-by: Sachin Kamat Cc: Thomas Abraham Cc: Mike Turquette --- Should be applied on top of the below patches: https://patchwork.kernel.org/patch/2448711/ https://patchwork.kernel.org/patch/2459831/ --- .../devicetree/bindings/clock/exynos4-clock.txt | 1 + drivers/clk/samsung/clk-exynos4.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index 14d5c2a..5b17c4d 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -236,6 +236,7 @@ Exynos4 SoC and this is specified where applicable. spi0_isp_sclk 380 Exynos4x12 spi1_isp_sclk 381 Exynos4x12 uart_isp_sclk 382 Exynos4x12 + tmu 383 [Mux Clocks] diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 09cf161..fc4f662 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -170,7 +170,7 @@ enum exynos4_clks { gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp, mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp, asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk, - spi1_isp_sclk, uart_isp_sclk, + spi1_isp_sclk, uart_isp_sclk, tmu, /* mux clocks */ mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0, @@ -815,6 +815,7 @@ static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"), GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), + GATE(tmu, "tmu", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 0), }; /* list of gate clocks supported in exynos4x12 soc */ @@ -915,6 +916,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, CLK_IGNORE_UNUSED, 0), GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), + GATE(tmu, "tmu", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 0), }; #ifdef CONFIG_OF