From patchwork Wed Mar 19 10:25:05 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 26551 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ig0-f197.google.com (mail-ig0-f197.google.com [209.85.213.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 875E3203C3 for ; Wed, 19 Mar 2014 10:31:45 +0000 (UTC) Received: by mail-ig0-f197.google.com with SMTP id hl1sf17922400igb.0 for ; Wed, 19 Mar 2014 03:31:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=+GPqyA9oRWruBdbX0j5UOC5GYowL+fWu3D3jxnYguLg=; b=ioInKmKlsyrnS1i94g37HVkR1Sq5/cpmuW5omfMf2ROTr2lzZzob+8XN1NOOsmWoPm 6IdCK0pVThIXbVflceXaUEakGgvBB8VDtcElYP6wUXuCogRfdnSrusuu/k0GfDbtbbMt wWJi8Rk7R4KBBxNRaHmUhA+AEaj8nySA07ydht9E0xQ804F+wjPJNFedC9uaHOd2oSoD Hy4R2z0jR+em3NCPjE3zmeGDY5/IBR0J4GL+WXTd8eGBN77In6Bo9yuhLp1UiYWryNFJ qtuZCC/PnSSND60/WL9pDKWwehMIVfZLfksOGw/cZwSKQBdo1xZRF4UtNda6mrvZe0V3 7pVQ== X-Gm-Message-State: ALoCoQnkqqWpihuSVSk4ukxfCC+rFYSj8j1HBsMt3+IS/M39YFUONurwOd9qqU53ZDFumx2FwTH8 X-Received: by 10.182.108.136 with SMTP id hk8mr1416004obb.11.1395225104955; Wed, 19 Mar 2014 03:31:44 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.102.1 with SMTP id v1ls2446488qge.50.gmail; Wed, 19 Mar 2014 03:31:44 -0700 (PDT) X-Received: by 10.220.114.135 with SMTP id e7mr12296480vcq.23.1395225104834; Wed, 19 Mar 2014 03:31:44 -0700 (PDT) Received: from mail-ve0-f177.google.com (mail-ve0-f177.google.com [209.85.128.177]) by mx.google.com with ESMTPS id m3si7546292vcr.23.2014.03.19.03.31.44 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 19 Mar 2014 03:31:44 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.177; Received: by mail-ve0-f177.google.com with SMTP id sa20so8394663veb.22 for ; Wed, 19 Mar 2014 03:31:44 -0700 (PDT) X-Received: by 10.58.90.99 with SMTP id bv3mr1169veb.34.1395225104741; Wed, 19 Mar 2014 03:31:44 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.78.9 with SMTP id i9csp287181vck; Wed, 19 Mar 2014 03:31:43 -0700 (PDT) X-Received: by 10.68.240.36 with SMTP id vx4mr17261706pbc.140.1395225102851; Wed, 19 Mar 2014 03:31:42 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id zm8si14628882pac.440.2014.03.19.03.31.42; Wed, 19 Mar 2014 03:31:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759126AbaCSKbj (ORCPT + 9 others); Wed, 19 Mar 2014 06:31:39 -0400 Received: from mail-pb0-f43.google.com ([209.85.160.43]:41498 "EHLO mail-pb0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758634AbaCSKbh (ORCPT ); Wed, 19 Mar 2014 06:31:37 -0400 Received: by mail-pb0-f43.google.com with SMTP id um1so8729231pbc.30 for ; Wed, 19 Mar 2014 03:31:36 -0700 (PDT) X-Received: by 10.69.25.69 with SMTP id io5mr39579717pbd.22.1395225096717; Wed, 19 Mar 2014 03:31:36 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id kc9sm60944281pbc.25.2014.03.19.03.31.33 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 19 Mar 2014 03:31:35 -0700 (PDT) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, mark.rutland@arm.com, sachin.kamat@linaro.org Subject: [PATCH Resend 3/3] ARM: EXYNOS: Map SYSRAM address through DT Date: Wed, 19 Mar 2014 15:55:05 +0530 Message-Id: <1395224705-2935-3-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1395224705-2935-1-git-send-email-sachin.kamat@linaro.org> References: <1395224705-2935-1-git-send-email-sachin.kamat@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: sachin.kamat@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Instead of hardcoding the SYSRAM details for each SoC, pass this information through device tree (DT) and make the code SoC agnostic. Signed-off-by: Sachin Kamat --- .../devicetree/bindings/arm/samsung-boards.txt | 11 +++ arch/arm/boot/dts/exynos4210-universal_c210.dts | 9 ++ arch/arm/boot/dts/exynos4210.dtsi | 10 ++ arch/arm/boot/dts/exynos4x12.dtsi | 10 ++ arch/arm/boot/dts/exynos5.dtsi | 5 + arch/arm/boot/dts/exynos5250.dtsi | 5 + arch/arm/boot/dts/exynos5420.dtsi | 5 + arch/arm/mach-exynos/common.c | 104 ++++++++------------ arch/arm/mach-exynos/include/mach/map.h | 7 -- 9 files changed, 95 insertions(+), 71 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung-boards.txt index 2168ed31e1b0..f79710eb7e79 100644 --- a/Documentation/devicetree/bindings/arm/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung-boards.txt @@ -7,6 +7,17 @@ Required root node properties: (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board. (b) "samsung,exynos4210" - for boards based on Exynos4210 SoC. + - sysram node, specifying the type (secure or non-secure) of SYSRAM + - compatible: following types are supported + "samsung,exynos4210-sysram" : Secure SYSRAM + "samsung,exynos4210-sysram-ns" : Non-secure SYSRAM + - reg: address of SYSRAM bank + + sysram@02020000 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x02020000 0x1000>; + }; + Optional: - firmware node, specifying presence and type of secure firmware: - compatible: only "samsung,secure-firmware" is currently supported diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index d2e3f5f5916d..b893a042e3f7 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -28,6 +28,15 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; }; + sysram@02020000 { + status = "disabled"; + }; + + sysram@02025000 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x02025000 0x1000>; + }; + mct@10050000 { compatible = "none"; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index cb0e768dc6d4..b92982b9607e 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -31,6 +31,16 @@ pinctrl2 = &pinctrl_2; }; + sysram@02020000 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x02020000 0x1000>; + }; + + sysram-ns@0203F000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x0203F000 0x1000>; + }; + pd_lcd1: lcd1-power-domain@10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index c4a9306f8529..d57e3120223f 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -37,6 +37,16 @@ interrupts = <2 2>, <3 2>, <18 2>, <19 2>; }; + sysram@02020000 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x02020000 0x1000>; + }; + + sysram-ns@0204F000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x0204F000 0x1000>; + }; + pd_isp: isp-power-domain@10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 79d0608d6dcc..c03bd09ec37d 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -18,6 +18,11 @@ / { interrupt-parent = <&gic>; + sysram@02020000 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x02020000 0x1000>; + }; + chipid@10000000 { compatible = "samsung,exynos4210-chipid"; reg = <0x10000000 0x100>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index fdeed7c29ac9..abfceadbb1ea 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -72,6 +72,11 @@ }; }; + sysram-ns@0204F000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x0204F000 0x1000>; + }; + pd_gsc: gsc-power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 82071154eb84..ea401d3b58e3 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -110,6 +110,11 @@ }; }; + sysram-ns@02073000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x02073000 0x1000>; + }; + clock: clock-controller@10010000 { compatible = "samsung,exynos5420-clock"; reg = <0x10010000 0x30000>; diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 10ed374c0744..d9ae5cd49194 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -129,51 +129,6 @@ static struct map_desc exynos4_iodesc[] __initdata = { }, }; -static struct map_desc exynos4_iodesc0[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSRAM, - .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos4_iodesc1[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSRAM, - .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos4210_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSRAM_NS, - .pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos4x12_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSRAM_NS, - .pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos5250_iodesc[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSRAM_NS, - .pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - static struct map_desc exynos5_iodesc[] __initdata = { { .virtual = (unsigned long)S3C_VA_SYS, @@ -196,11 +151,6 @@ static struct map_desc exynos5_iodesc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)S5P_VA_SYSRAM, - .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM), - .length = SZ_4K, - .type = MT_DEVICE, - }, { .virtual = (unsigned long)S5P_VA_CMU, .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), .length = 144 * SZ_1K, @@ -291,6 +241,44 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, return 1; } +struct __sysram_desc { + char name[32]; + unsigned long addr; +}; + +static struct __sysram_desc sysram_desc[] __initdata = { + { + .name = "samsung,exynos4210-sysram", + .addr = (unsigned long)S5P_VA_SYSRAM, + }, { + .name = "samsung,exynos4210-sysram-ns", + .addr = (unsigned long)S5P_VA_SYSRAM_NS, + }, +}; + +static int __init exynos_fdt_map_sysram(unsigned long node, const char *uname, + int depth, void *data) +{ + struct map_desc iodesc; + __be32 *reg; + unsigned long len; + int i; + + for (i = 0; i < ARRAY_SIZE(sysram_desc); i++) { + if (of_flat_dt_is_compatible(node, sysram_desc[i].name)) { + reg = of_get_flat_dt_prop(node, "reg", &len); + if (!reg || len != (sizeof(unsigned long) * 2)) + return -ENODEV; + iodesc.virtual = sysram_desc[i].addr; + iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0])); + iodesc.length = be32_to_cpu(reg[1]); + iodesc.type = MT_DEVICE; + iotable_init(&iodesc, 1); + } + } + return 0; +} + /* * exynos_map_io * @@ -303,20 +291,6 @@ static void __init exynos_map_io(void) if (soc_is_exynos5250() || soc_is_exynos5420()) iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); - - if (soc_is_exynos4210()) { - if (samsung_rev() == EXYNOS4210_REV_0) - iotable_init(exynos4_iodesc0, - ARRAY_SIZE(exynos4_iodesc0)); - else - iotable_init(exynos4_iodesc1, - ARRAY_SIZE(exynos4_iodesc1)); - iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc)); - } - if (soc_is_exynos4212() || soc_is_exynos4412()) - iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc)); - if (soc_is_exynos5250()) - iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc)); } void __init exynos_init_io(void) @@ -329,6 +303,8 @@ void __init exynos_init_io(void) s5p_init_cpu(S5P_VA_CHIPID); exynos_map_io(); + + of_scan_flat_dt(exynos_fdt_map_sysram, NULL); } struct bus_type exynos_subsys = { diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 7b046b59d9ec..548269a60634 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -23,13 +23,6 @@ #include -#define EXYNOS4_PA_SYSRAM0 0x02025000 -#define EXYNOS4_PA_SYSRAM1 0x02020000 -#define EXYNOS5_PA_SYSRAM 0x02020000 -#define EXYNOS4210_PA_SYSRAM_NS 0x0203F000 -#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000 -#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000 - #define EXYNOS_PA_CHIPID 0x10000000 #define EXYNOS4_PA_SYSCON 0x10010000