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[209.132.180.67]) by mx.google.com with ESMTP id fo3si11610666pad.223.2014.05.19.20.52.15; Mon, 19 May 2014 20:52:15 -0700 (PDT) Received-SPF: none (google.com: linux-samsung-soc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750922AbaETDwP (ORCPT + 9 others); Mon, 19 May 2014 23:52:15 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:33865 "EHLO mail-pa0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750763AbaETDwO (ORCPT ); Mon, 19 May 2014 23:52:14 -0400 Received: by mail-pa0-f54.google.com with SMTP id bj1so6713033pad.27 for ; Mon, 19 May 2014 20:52:14 -0700 (PDT) X-Received: by 10.68.139.71 with SMTP id qw7mr46975831pbb.68.1400557934069; Mon, 19 May 2014 20:52:14 -0700 (PDT) Received: from linaro.sisodomain.com ([14.140.216.146]) by mx.google.com with ESMTPSA id id10sm437284pbc.35.2014.05.19.20.52.11 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 19 May 2014 20:52:13 -0700 (PDT) From: Tushar Behera To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, tomasz.figa@gmail.com, Sachin Kamat Subject: [PATCH V2 1/2] ARM: EXYNOS: Update secondary boot addr for secure mode Date: Tue, 20 May 2014 09:20:09 +0530 Message-Id: <1400557810-28428-1-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: tushar.behera@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Sachin Kamat Almost all Exynos-series of SoCs that run in secure mode don't need additional offset for every CPU, with Exynos4412 being the only exception. Tested on Origen-Quad (Exynos4412) and Arndale-Octa (Exynos5420). While at it, fix the coding style (space around *). Signed-off-by: Sachin Kamat Signed-off-by: Tushar Behera --- Changes for V2: * Changed the condition statement as per review comment * Fixed coding style arch/arm/mach-exynos/firmware.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 739bdc8..7d18103 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -50,8 +50,13 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) boot_reg = sysram_ns_base_addr + 0x1c; - if (!soc_is_exynos4212()) - boot_reg += 4*cpu; + /* + * Almost all Exynos-series of SoCs that run in secure mode don't need + * additional offset for every CPU, with Exynos4412 being the only + * exception. + */ + if (soc_is_exynos4412()) + boot_reg += 4 * cpu; __raw_writel(boot_addr, boot_reg); return 0;