From patchwork Tue Nov 25 06:21:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 41450 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ee0-f69.google.com (mail-ee0-f69.google.com [74.125.83.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id A6F2325E18 for ; Tue, 25 Nov 2014 06:22:05 +0000 (UTC) Received: by mail-ee0-f69.google.com with SMTP id d49sf121307eek.4 for ; Mon, 24 Nov 2014 22:22:04 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:sender:precedence:list-id:x-original-sender :x-original-authentication-results:mailing-list:list-post:list-help :list-archive:list-unsubscribe; bh=ZcVboOrxop2n/hzs9q7oAjrrRZnY110mdfUF/lMvoHQ=; b=jnWyHl7Au8amRLht5qNPSCUeSwyfQL5oMI1ppB/0QwGlffCpFfd4HwWOPFNVNXwK+X 99a3jU2uV5PPzPHAvD8JtQHX0a0+JmjwjkA4Ibb3HBu3xHlI9/RpkgNddlqJNhkBJhJA aU05ixVWSIGjMrnvE9yQ0OFpB45yjszsDYLJ3dMRV3hwXqVPF/txChbLHK5NJoSjbtSp wFPBy+ol/1fS+kwxGfaPF3I7k8TsYmdhGtOY8GW1OmKWmUSkRB8J6lRXvjl1H+is7zYF yQetAJM4BYcd4rpJ0GowPtJ+eDr8ZEEEPO91JNi0vb+TD1n23yEPM/admwzjbpd0vbpQ 5kQw== X-Gm-Message-State: ALoCoQkIUoK7j98w3d02sXNqMOQHtozxtx4GC0fK0ly4p51FqkzlkuYwRgJ8niKKhvPUVL5ct0R6 X-Received: by 10.112.142.36 with SMTP id rt4mr7184449lbb.3.1416896524901; Mon, 24 Nov 2014 22:22:04 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.21.71 with SMTP id t7ls496290lae.11.gmail; Mon, 24 Nov 2014 22:22:04 -0800 (PST) X-Received: by 10.152.29.41 with SMTP id g9mr24575313lah.83.1416896524690; Mon, 24 Nov 2014 22:22:04 -0800 (PST) Received: from mail-lb0-f169.google.com (mail-lb0-f169.google.com. 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[209.132.180.67]) by mx.google.com with ESMTP id nt6si467902pbb.13.2014.11.24.22.22.01 for ; Mon, 24 Nov 2014 22:22:01 -0800 (PST) Received-SPF: none (google.com: linux-samsung-soc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750840AbaKYGVz (ORCPT + 4 others); Tue, 25 Nov 2014 01:21:55 -0500 Received: from mail.kernel.org ([198.145.19.201]:59421 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751935AbaKYGVy (ORCPT ); Tue, 25 Nov 2014 01:21:54 -0500 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 94E66200E9; Tue, 25 Nov 2014 06:21:52 +0000 (UTC) Received: from localhost (c-67-160-101-93.hsd1.wa.comcast.net [67.160.101.93]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 576BC201CE; Tue, 25 Nov 2014 06:21:51 +0000 (UTC) From: Kevin Hilman To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linaro-kernel@lists.linaro.org, Olof Johansson , Mauro Ribeiro , Abhilash Kesavan , Andrew Bresticker , Doug Anderson , Nicolas Pitre Subject: [RFC] ARM: exynos: MCPM: [is this a] fix for secondary boot on 5422? Date: Mon, 24 Nov 2014 22:21:50 -0800 Message-Id: <1416896510-24612-1-git-send-email-khilman@kernel.org> X-Mailer: git-send-email 2.1.3 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Kevin Hilman Using the current exynos_defconfig on the exynos5422-odroid-xu3, only 6 of 8 CPUs come online with MCPM boot. CPU0 is an A7, CPUs 1-4 are A15s and CPU5-7 are the other A7s, but with the current code, CPUs 5 and 7 do not boot: [...] Exynos MCPM support installed CPU1: update cpu_capacity 1535 CPU1: thread -1, cpu 0, socket 0, mpidr 80000000 CPU2: update cpu_capacity 1535 CPU2: thread -1, cpu 1, socket 0, mpidr 80000001 CPU3: update cpu_capacity 1535 CPU3: thread -1, cpu 2, socket 0, mpidr 80000002 CPU4: update cpu_capacity 1535 CPU4: thread -1, cpu 3, socket 0, mpidr 80000003 CPU5: failed to come online CPU6: update cpu_capacity 448 CPU6: thread -1, cpu 2, socket 1, mpidr 80000102 CPU7: failed to come online Brought up 6 CPUs CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x13) CPU: This may indicate a broken bootloader or firmware. Thanks to a tip from Abhilash, this patch gets all 8 CPUs booting again, but the warning about CPUs started in inconsistent modes remains. Also, not being terribly familiar with Exynos internals, it's not at all obvious to me why this register write (done for *all* secondaries) makes things work works for the 2 secondary CPUs that didn't come online. It's also not obvious whether this is the right general fix, since it doesn't seem to be needed on other 542x or 5800 platforms. I suspect the "right" fix is in the bootloader someplace, but not knowing this hardware well, I'm not sure if the fix is in u-boot proper, or somewhere in the binary blobs (bl1/bl2/tz) that start before u-boot. The u-boot I'm using is from the hardkernel u-boot repo[1], and I'd welcome any suggestions to try. I'm able to rebuild my own u-boot from there, but only have binaries for bl1/bl2/tz. [1] branch "odroidxu3-v2012.07" of: https://github.com/hardkernel/u-boot.git Cc: Mauro Ribeiro Cc: Abhilash Kesavan , Cc: Andrew Bresticker Cc: Doug Anderson Cc: Nicolas Pitre Signed-off-by: Kevin Hilman --- arch/arm/mach-exynos/mcpm-exynos.c | 2 ++ arch/arm/mach-exynos/regs-pmu.h | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index b0d3c2e876fb..612a770d5284 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -88,6 +88,8 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster) cluster >= EXYNOS5420_NR_CLUSTERS) return -EINVAL; + pmu_raw_writel(0x1, S5P_PMU_SPARE2); + /* * Since this is called with IRQs enabled, and no arch_spin_lock_irq * variant exists, we need to disable IRQs manually here. diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index b5f4406fc1b5..70d9eb5a4fcc 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -49,6 +49,7 @@ #define S5P_INFORM5 0x0814 #define S5P_INFORM6 0x0818 #define S5P_INFORM7 0x081C +#define S5P_PMU_SPARE2 0x0908 #define S5P_PMU_SPARE3 0x090C #define EXYNOS_IROM_DATA2 0x0988