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Thu, 22 Dec 2016 23:17:55 +0900 (KST) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH] ARM: dts: exynos: Add audio power domain support to Exynos542x SoCs Date: Thu, 22 Dec 2016 15:17:44 +0100 Message-id: <1482416264-12169-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJIsWRmVeSWpSXmKPExsWy7bCmhu7UB9ERBjues1psnLGe1eL8+Q3s FjPO72OyWHvkLrvF4TftrA6sHptWdbJ59G1ZxejxeZNcAHMUl01Kak5mWWqRvl0CV8ad7RkF v/kr1q69ztrAeJqni5GTQ0LAROLviU5GCFtM4sK99WxdjFwcQgJLGSWWNp1jhHDamSSOPbnB CtOxbOpKMFtIYDmjxMz9mhBFvxgltkzYywySYBMwlOh628UGYosIqEp8blvADlLELLCXUeLQ tEawhLBAmMSVF7vAbBagovWX94E18wp4SNy5/Qpqm5zEyWOTWUGaJQR2sEncedwDVMQB5MhK bDrADFHjIjHr7RomCFtY4tXxLewQtrTE36W3oH7rZ5RoatWGsGcwSpx7ywthW0scPn4RbBez AJ9E7+8nTBDjeSU62oQgSjwk9n+eyAJhO0ocfv8c6vlYiXuvdrBMYJRewMiwilEstaA4Nz21 2LTARK84Mbe4NC9dLzk/dxMjOAK1InYw/psRdIhRgINRiYfXoTQ6Qog1say4MvcQowQHs5II 7+Y7QCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8CyqsI4QE0hNLUrNTUwtSi2CyTBycUg2M1cK1 ijaGK0tUD0+W4bodm9/aeIDj5bHNm9S2bpnx7ldG2ucm0wMR/5hjZdRfLs2X/fBLeucNy8tS y56HLjSomqGesujYt7b3+3bYy4Sce7FTvte3S0U3tS/F2O2igI1v/FTO41Fz7rA3hs6Rf6p2 /+u8hjl9fWcZhKSWpcls3fg56cxEx+IPSizFGYmGWsxFxYkAFCa2K7wCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrILMWRmVeSWpSXmKPExsVy+t9jAd3JD6IjDJY8MrTYOGM9q8X58xvY LWac38dksfbIXXaLw2/aWR1YPTat6mTz6NuyitHj8ya5AOYoN5uM1MSU1CKF1Lzk/JTMvHRb pdAQN10LJYW8xNxUW6UIXd+QICWFssScUiDPyAANODgHuAcr6dsluGXc2Z5R8Ju/Yu3a66wN jKd5uhg5OSQETCSWTV3JCmGLSVy4t56ti5GLQ0hgKaPEl9PHoJxfjBIPz3eygFSxCRhKdL3t YgOxRQRUJT63LWAHKWIW2M8ocX7rM2aQhLBAmMTJHacZQWwWoKL1l/eBxXkFPCTu3H4FtU5O 4uSxyawTGLkXMDKsYpRILUguKE5KzzXKSy3XK07MLS7NS9dLzs/dxAgOvmfSOxgP73I/xCjA wajEw3uCOzpCiDWxrLgy9xCjBAezkgjv5jtAId6UxMqq1KL8+KLSnNTiQ4ymQAdMZJYSTc4H RkZeSbyhibmJubGBhbmlpYmRkjhv4+xn4UIC6YklqdmpqQWpRTB9TBycUg2Mx8RP8qXoh71Q mrw7zW7R41SPPXOv1YuZr246tao2KaH22CKWB/c3G2T0usfKtN0vmmAn8p/3eJuYQdWyp2YR nm4lIavjnPcHid1//qvA3s5Pq+TVwqksd2wC9PfpVMccFcnP8Eo4/0zLo2HtsXsCf8wcfN5p 31Xm+1v5N+U8f3lllblnxHklluKMREMt5qLiRADr7fUFVAIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20161222141755epcas5p4549c18c84aa823c553bb33a12eb82ee2 X-Msg-Generator: CA X-Sender-IP: 203.254.230.27 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 105P X-HopCount: 7 X-CMS-RootMailID: 20161222141755epcas5p4549c18c84aa823c553bb33a12eb82ee2 X-RootMTR: 20161222141755epcas5p4549c18c84aa823c553bb33a12eb82ee2 References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Audio power domain includes following hardware modules: Pin controller for GPZ bank, AudioSS clock controller, PL330 ADMA device and Exynos I2S controller. Signed-off-by: Marek Szyprowski --- Currently this domain will not be turned off, because pinctrl and clock controller don't support runtime PM and PL330 ADMA requires irq-safe runtime PM. Separate patches for those devices/subsystems will be posted to get proper runtime PM available and finally let this power domain to be turned off. --- arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 0154c2e..d9ebc33 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -188,6 +188,7 @@ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; + power-domains = <&mau_pd>; }; mfc: codec@11000000 { @@ -317,6 +318,12 @@ clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; }; + mau_pd: power-domain@100440E0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440E0 0x20>; + #power-domain-cells = <0>; + }; + pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5420-pinctrl"; reg = <0x13400000 0x1000>; @@ -351,6 +358,7 @@ compatible = "samsung,exynos5420-pinctrl"; reg = <0x03860000 0x1000>; interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mau_pd>; }; amba { @@ -369,6 +377,7 @@ #dma-cells = <1>; #dma-channels = <6>; #dma-requests = <16>; + power-domains = <&mau_pd>; }; pdma0: pdma@121A0000 { @@ -441,6 +450,7 @@ samsung,idma-addr = <0x03000000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + power-domains = <&mau_pd>; status = "disabled"; };