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Thu, 26 Jan 2017 12:43:48 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH] clk: samsung: exynos5433: Correct typos in SoC name Date: Thu, 26 Jan 2017 13:43:42 +0100 Message-id: <1485434622-6936-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHIsWRmVeSWpSXmKPExsWy7djP87qs7zsjDL6u5rDYOGM9q8X1L89Z Lc6f38BuMeP8PiaLtUfuslscftPO6sDmsWlVJ5tH35ZVjB6fN8kFMEdx2aSk5mSWpRbp2yVw Zez8eoel4LNGxcY7f9kaGD8rdTFyckgImEi8e9vPAmGLSVy4t56ti5GLQ0hgKaPEope97BDO Z0aJ2Y0bWWE6TjetYYJILGOUWDbjLlRVA5PEk6sdzCBVbAKGEl1vu9hAbBEBVYnPbQvAipgF njJK3FvcwgSSEBZwkdh5bz9YAwtQ0ZKzv8BW8Aq4Szyc+p4RYp2cxMljk1lBmiUEDrBJfF65 F6iZA8iRldh0gBmixkXizfOFbBC2sMSr41vYIWwZic6Og0wQdj+jRFOrNoQ9g1Hi3FteCNta 4vDxi2B7mQX4JCZtm84MMZ5XoqNNCKLEQ2JP8y2o8Y4Sbe8bwOElJBAr0bX4IdsERukFjAyr GEVSS4tz01OLjfSKE3OLS/PS9ZLzczcxAmPx9L/jH3cwvj9hdYhRgINRiYf3wI6OCCHWxLLi ytxDjBIczEoivJvedkYI8aYkVlalFuXHF5XmpBYfYpTmYFES592z4Eq4kEB6YklqdmpqQWoR TJaJg1OqgTF0xwUBoen6ybGJPx0/lGyvNIw/d+oP05F036o4aTevhYaX6hL+7deMZzj6tWrJ RbZfr4/1rIrZ5/vrqEt5urFFkDkT47y/04N2rFS5d8puiqr3QZ2T+x2V8/l2rQwpPFPHUNS1 aYXbto+J72pPec43qopbpbTMOGqn7OeHeY71ZimGmnw7mZRYijMSDbWYi4oTAakwcmjBAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMLMWRmVeSWpSXmKPExsVy+t/xK7ou7zsjDE5tNrLYOGM9q8X1L89Z Lc6f38BuMeP8PiaLtUfuslscftPO6sDmsWlVJ5tH35ZVjB6fN8kFMEe52WSkJqakFimk5iXn p2TmpdsqhYa46VooKeQl5qbaKkXo+oYEKSmUJeaUAnlGBmjAwTnAPVhJ3y7BLWPn1zssBZ81 Kjbe+cvWwPhZqYuRk0NCwETidNMaJghbTOLCvfVsXYxcHEICSxglJrb2skM4TUwSSy79YgSp YhMwlOh628UGYosIqEp8blsAVsQs8JxR4v3ufhaQhLCAi8TOe/uZQWwWoKIlZ3+xgti8Au4S D6e+Z4RYJydx8thk1gmM3AsYGVYxiqSWFuem5xYb6hUn5haX5qXrJefnbmIEBuC2Yz8372C8 tDH4EKMAB6MSD++BHR0RQqyJZcWVuYcYJTiYlUR4N73tjBDiTUmsrEotyo8vKs1JLT7EaAq0 fCKzlGhyPjA68kriDU0MzS0NjYwtLMyNjJTEeUs+XAkXEkhPLEnNTk0tSC2C6WPi4JRqYAzj eMmUYG+/RmLrgwulP9zWLle9vvZc1afT+2+YdldP3VxtE7zfJSAzSLjcjK3YM+/pZJUrU2/X l7Bk3n/1R+RtU6FZ7LSwjtQZvxbsM7Yo4r2aVmhrJ1rcWf2xJ3FF++bOC8UWOfU12RMm5HH0 CGpOc372ksnyoPBhRYNLv/N8oqUjY8RdlFiKMxINtZiLihMBg2BczlYCAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170126124348eucas1p19cd1a8f28f657f523ac46b48bf699674 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170126124348eucas1p19cd1a8f28f657f523ac46b48bf699674 X-RootMTR: 20170126124348eucas1p19cd1a8f28f657f523ac46b48bf699674 References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch fixes simple typos in Exynos5433 clocks driver. The SoC name was refered a few times as '5443' instead of '5433'. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos5433.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Chanwoo Choi Reviewed-by: Krzysztof Kozlowski diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 0db5204c307c..8fd7f6e88e3c 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -6,7 +6,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Common Clock Framework support for Exynos5443 SoC. + * Common Clock Framework support for Exynos5433 SoC. */ #include @@ -698,7 +698,7 @@ * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL */ -static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst = { +static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = { PLL_35XX_RATE(2500000000U, 625, 6, 0), PLL_35XX_RATE(2400000000U, 500, 5, 0), PLL_35XX_RATE(2300000000U, 575, 6, 0), @@ -749,7 +749,7 @@ }; /* AUD_PLL */ -static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] __initconst = { +static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = { PLL_36XX_RATE(400000000U, 200, 3, 2, 0), PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), PLL_36XX_RATE(384000000U, 128, 2, 2, 0), @@ -764,9 +764,9 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", - ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates), + ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates), PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", - AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates), + AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates), }; static const struct samsung_cmu_info top_cmu_info __initconst = { @@ -820,7 +820,7 @@ static void __init exynos5433_cmu_top_init(struct device_node *np) static const struct samsung_pll_clock cpif_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", - MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates), + MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates), }; static const struct samsung_mux_clock cpif_mux_clks[] __initconst = { @@ -1011,13 +1011,13 @@ static void __init exynos5433_cmu_cpif_init(struct device_node *np) static const struct samsung_pll_clock mif_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", - MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates), + MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates), PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", - MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates), + MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates), PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk", - BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates), + BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates), PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk", - MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates), + MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates), }; /* list of all parent clock list */ @@ -2539,7 +2539,7 @@ static void __init exynos5433_cmu_g2d_init(struct device_node *np) static const struct samsung_pll_clock disp_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", - DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates), + DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates), }; static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = { @@ -3224,7 +3224,7 @@ static void __init exynos5433_cmu_aud_init(struct device_node *np) static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", - G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates), + G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates), }; static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { @@ -3514,7 +3514,7 @@ static void __init exynos5433_cmu_gscl_init(struct device_node *np) static const struct samsung_pll_clock apollo_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", - APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates), + APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates), }; static const struct samsung_mux_clock apollo_mux_clks[] __initconst = { @@ -3737,7 +3737,7 @@ static void __init exynos5433_cmu_apollo_init(struct device_node *np) static const struct samsung_pll_clock atlas_pll_clks[] __initconst = { PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk", - ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates), + ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates), }; static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {