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Tue, 22 Jun 2021 13:02:02 +0000 (GMT) From: Alim Akhtar To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org Cc: krzysztof.kozlowski@canonical.com, linux-samsung-soc@vger.kernel.org, Alim Akhtar Subject: [PATCH v2 1/2] arm64: dts: exynos7: Add cpu cache information Date: Tue, 22 Jun 2021 18:35:50 +0530 Message-Id: <20210622130551.67446-1-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrAIsWRmVeSWpSXmKPExsWy7bCmui73g4sJBnu+C1s8mLeNzWLj2x9M FpseX2O1uLxrDpvFjPP7mCxa9x5hd2DzmNXQy+axaVUnm8fmJfUefVtWMXp83iQXwBrFZZOS mpNZllqkb5fAlbH/1RzGgq+CFUdvKDcwvuTtYuTkkBAwkWh93sbexcjFISSwm1Fi2qQeRgjn E6PEpolNbBDOZ0aJne97mWBadt/7zgSR2MUoseRGCztIQkighUli84Q0EJtNQFvi7vQtYA0i AjESD/fMYwWxmQUKJV603ASrFxZwk+hddIsZxGYRUJX4O2stC4jNK2Aj0d35nR1imbzE6g0H mEGWSQgsY5fY0HwE6goXicWdq1kgbGGJV8e3QDVISbzsB3mIA8jOlujZZQwRrpFYOu8YVLm9 xIErc1hASpgFNCXW79KHCMtKTD21jgniTD6J3t9PoDbxSuyYB2OrSjS/uwo1RlpiYnc3K4Tt ITGp+yULJBhiJU48Wco4gVF2FsKGBYyMqxglUwuKc9NTi00LjPNSy/WKE3OLS/PS9ZLzczcx giNdy3sH46MHH/QOMTJxMB5ilOBgVhLhfZF9MUGINyWxsiq1KD++qDQntfgQozQHi5I471L2 QwlCAumJJanZqakFqUUwWSYOTqkGponb/uqHCFvpKGnqbhNYpjLVMvXS0UvGYlWHMx5GnAkp uv/u8Z/ElsCXj0o4Y8268z/PP8Y+Mem4zR3pVNcM/ZMPnMwsGO9m/75Q/YP12/PswMxrHVtc z30SqyyQPpz8YPM+wZIKd3vmwu03j17xedd+I9DgS9OyPb6Kok/vCe2ewbM7SeLt6ZAI8Qxf xZ03ExRnOxw1C9BilL+nYbPXdNPfucs2Kn7if/5mo6Hjh0XHgu89DLkofdObactM2RdzRUzd xTi9y/9KLDCYxdu16qzu1T4Gs59vZn0RFPbJvb3nbnrtO6+62WtO+4nobLN4/zns3Kunvmlb 3l2tlJtw+P+/VIa6/23SfZfdenesXarEUpyRaKjFXFScCABBGCO7YwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGJMWRmVeSWpSXmKPExsWy7bCSnK73/YsJBvtWilg8mLeNzWLj2x9M FpseX2O1uLxrDpvFjPP7mCxa9x5hd2DzmNXQy+axaVUnm8fmJfUefVtWMXp83iQXwBrFZZOS mpNZllqkb5fAlbH/1RzGgq+CFUdvKDcwvuTtYuTkkBAwkdh97ztTFyMXh5DADkaJu8tPskAk pCWub5zADmELS6z895wdoqiJSeLC0gdMIAk2AW2Ju9O3ANkcHCICcRKt66tBTGaBYonTv8Aq hAXcJHoX3WIGsVkEVCX+zloLNp5XwEaiu/M71Hh5idUbDjBPYORZwMiwilEytaA4Nz232LDA KC+1XK84Mbe4NC9dLzk/dxMjOGi0tHYw7ln1Qe8QIxMH4yFGCQ5mJRHeF9kXE4R4UxIrq1KL 8uOLSnNSiw8xSnOwKInzXug6GS8kkJ5YkpqdmlqQWgSTZeLglGpgSp24JLh4f3rS4ikLZix7 /MQxPWtytOrRQ7POMDPq397G08ltKaA/raxH9XLQoaPSiTcDKu/GbRMJF1397++H60smH946 8Z3ArFY1teJ3JS92/4lZcc/t1oIFmxzkf1kcq3M0U96UvUxk4wH7gsTHXF3vz+r4RDWtjXgX 7Gk4sTq8pbo5bqvyvYflfhl76zbkbE/grpryafuTsh3zbjNMmviw0ZBrg43FUXlvVyt+Fb0P 5y1XMDq+PmG0mONa13Gu6c83bb9bJhQimyn96pRF+WaHTeXHQkSWvvjIIfBdlHVycjHze6XX JgwChysZDj1crXlo13m1/8++ip+ey9st77i5YIXymQ5R4/R7G5+aBCuxFGckGmoxFxUnAgBr bFoMiQIAAA== X-CMS-MailID: 20210622130203epcas5p48a3111fc6586b1bfe0bd3cb90f783ce0 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20210622130203epcas5p48a3111fc6586b1bfe0bd3cb90f783ce0 References: Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch adds cpu caches information to its dt nodes so that the same is available to userspace via sysfs. This SoC has 48/32 KB I/D cache for each cores and 2MB of L2 cache. Signed-off-by: Alim Akhtar --- Changes since v1: * no change in this patch * changes as per Krzysztof's review comments in patch 2/2 arch/arm64/boot/dts/exynos/exynos7.dtsi | 35 +++++++++++++++++++++++++ 1 file changed, 35 insertions(+) base-commit: 614124bea77e452aa6df7a8714e8bc820b489922 diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 10244e59d56d..8b06397ba6e7 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -54,6 +54,13 @@ compatible = "arm,cortex-a57"; reg = <0x0>; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&atlas_l2>; }; cpu_atlas1: cpu@1 { @@ -61,6 +68,13 @@ compatible = "arm,cortex-a57"; reg = <0x1>; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&atlas_l2>; }; cpu_atlas2: cpu@2 { @@ -68,6 +82,13 @@ compatible = "arm,cortex-a57"; reg = <0x2>; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&atlas_l2>; }; cpu_atlas3: cpu@3 { @@ -75,6 +96,20 @@ compatible = "arm,cortex-a57"; reg = <0x3>; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&atlas_l2>; + }; + + atlas_l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; }; };