From patchwork Thu Oct 7 19:41:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 515472 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp1482473ime; Thu, 7 Oct 2021 12:41:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyt4fjRMWCHmMoeUQQxdDFOB+XUZwjKU9F+tAzTVT8pus5VQyMrZkCkCtdFfCwZ/DEnmSbP X-Received: by 2002:a05:6402:5244:: with SMTP id t4mr8996980edd.14.1633635688614; Thu, 07 Oct 2021 12:41:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633635688; cv=none; d=google.com; s=arc-20160816; b=OlW9DNmc9p5QlNGcjIQVn8UZITMJ5r1l27lxGPPqigw1Ae0tJFJo3HimKn0a18AdI4 TfhHjDb9g6TH5LZEvU/EPKWJSGOOXLKnj+cXoJv9Kv4mPP3kAojj2j8gOgBZ9HG9mXkG tixWvhjHoDCkcTfXjHaC9rZBIaJCzfn1H5qJafOQPbMmCeGuX/q4DMi5Qtc5ZwuB7jYz p56NjylniMafeMjXshKqI0Pev8JSDFT9idnXV8IV9O27eMGSAlXXjxaqP8miOaN3f5Rv O6kHDNeoSufrF4gSZtDA3ocsqZ6+i3jgw7dmTAo0LC8u7lXKvxcWOgO0QLeHdHIFRHk6 mtcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ix/+t+gee+jLY4mEvvcEKIS0I2uhnEhpLTqn69/kXXo=; b=IwCd284K9b67hPXiBg6Cp0hwNi8DdhfcSmtN/NE68MtL6+x1QIERwgZr00xggNGq5m WoTJf0VpJw2V33X/nJEl8VDAYBUj/vtJfAfbxCTtDOScF9B0Gk06JxPCQqiKy1DEWQC8 3gIQ2D6Ks/Oobvb/r8ZELqO9oOYOf0KMpS5NfaNTJHIl3OaDfZZJWuyvw/G+t7pNfjEV sFwlRSjRVtyGTIklePX4gMIuR/Y8TZ+wB15MEy8Ytg7iUaZcXxvvVhkTP1dzbXJ8G2sn xoGarVYsihGoish5g3qNeH9JNKosyo5zl+PmBgrs2i11kL8pkn7OuzTamVE4gk618XCC gNFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yerk9gii; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id x96si310320ede.219.2021.10.07.12.41.28; Thu, 07 Oct 2021 12:41:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yerk9gii; spf=pass (google.com: domain of linux-samsung-soc-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233354AbhJGTnU (ORCPT + 4 others); Thu, 7 Oct 2021 15:43:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232940AbhJGTnM (ORCPT ); Thu, 7 Oct 2021 15:43:12 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 908EEC061570 for ; Thu, 7 Oct 2021 12:41:18 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id y15so29488345lfk.7 for ; Thu, 07 Oct 2021 12:41:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ix/+t+gee+jLY4mEvvcEKIS0I2uhnEhpLTqn69/kXXo=; b=yerk9gii9Yt/opJeS2cABRXKJXB6Kag06gzjeaxccuQdAA55Irt28TtHpN5h4ANCXg n1e+sosf07UhGWUtrxjduGfP+9jQmTSO91sFLSKFQromE8ri/k+NDUYacu7KbfvXDDtp f4E2b4XlSiAyqZlCzoslUh5xWfnWzXlpCR/UfUnccro4Cmw0EEpe8zMPb+bOaviEK80X 2rXh3NPj9mORk/i1bfpbdZndm7yekxk1pNZTFRiIpwFmWbrKBhD1Tq6SAjDFysQaYwPa zeHGqjFJUHYhY0cP0aDrwHhT652XU3iAozdnXjeJiEK3HZ5SQaiYA8nvayKxzRMG/B1e wJ9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ix/+t+gee+jLY4mEvvcEKIS0I2uhnEhpLTqn69/kXXo=; b=ieV6pOUOOTeIAaC1DkA1BQ9fKDeDBqDECZRnvJWat+v5wmRN5LYl6D5BCQIai2HWW+ cjA0V6HZVtXD2sEjzmDcT057Slt/nuapaMz/tCXwneF7Nk73poBRF6YJJteLCM/bV7Nw LyRzKxH02SdqbUDtotHcW+bk8PRcKnGRArBSYfplMwVPRDfYLYfxR2tTxCcbZvNjn0pv jy5saKQ8ZZWUN871gtMAsypvhcknNBa1mzK/GFFuRb5b9B4mN0/3S6zWKgz6qR8H+zQz tSRcE+MxYXX0w+yAsTbJviKUlQKHGaF2eM0euhH4uSkmBcXeXN9z855s90zGs1MCnk8/ 8gog== X-Gm-Message-State: AOAM532fiADLb3wrbcnvRpZEAn4A9Ke3y0J2y/SCO40vEi/5lAz9rZzV opA6dmHvTOE1dm3pAJFa/DiwJw== X-Received: by 2002:a05:6512:3409:: with SMTP id i9mr5887576lfr.165.1633635676933; Thu, 07 Oct 2021 12:41:16 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id m25sm25631lji.52.2021.10.07.12.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Oct 2021 12:41:16 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , =?utf-8?q?Pawe=C5=82_Chmiel?= , Chanwoo Choi , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette Cc: Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v2 1/5] clk: samsung: clk-pll: Implement pll0822x PLL type Date: Thu, 7 Oct 2021 22:41:09 +0300 Message-Id: <20211007194113.10507-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20211007194113.10507-1-semen.protsenko@linaro.org> References: <20211007194113.10507-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org pll0822x PLL is used in Exynos850 SoC for top-level integer PLLs. The code was derived from very similar pll35xx type, with next differences: 1. Lock time for pll0822x is 150*P_DIV, when for pll35xx it's 270*P_DIV 2. It's not suggested in Exynos850 TRM that S_DIV change doesn't require performing PLL lock procedure (which is done in pll35xx implementation) When defining pll0822x type, CON3 register offset should be provided as a "con" parameter of PLL() macro, like this: PLL(pll_0822x, 0, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, exynos850_shared0_pll_rates), To define PLL rates table, one can use PLL_35XX_RATE() macro, e.g.: PLL_35XX_RATE(26 * MHZ, 1600 * MHZ, 800, 13, 0) as it's completely appropriate for pl0822x type and there is no sense in duplicating that. If bit #1 (MANUAL_PLL_CTRL) is not set in CON1 register, it won't be possible to set new rate, with next error showing in kernel log: Could not lock PLL fout_shared1_pll That can happen for example if bootloader clears that bit beforehand. PLL driver doesn't account for that, so if MANUAL_PLL_CTRL bit was cleared, it's assumed it was done for a reason and it shouldn't be possible to change that PLL's rate at all. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski Acked-by: Chanwoo Choi --- Changes in v2: - Added R-b tag by Krzysztof Kozlowski - Added Ack tag by Chanwoo Choi drivers/clk/samsung/clk-pll.c | 91 +++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 92 insertions(+) -- 2.30.2 diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 5873a9354b50..03131b149c0b 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -415,6 +415,89 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = { .recalc_rate = samsung_pll36xx_recalc_rate, }; +/* + * PLL0822x Clock Type + */ +/* Maximum lock time can be 150 * PDIV cycles */ +#define PLL0822X_LOCK_FACTOR (150) + +#define PLL0822X_MDIV_MASK (0x3FF) +#define PLL0822X_PDIV_MASK (0x3F) +#define PLL0822X_SDIV_MASK (0x7) +#define PLL0822X_MDIV_SHIFT (16) +#define PLL0822X_PDIV_SHIFT (8) +#define PLL0822X_SDIV_SHIFT (0) +#define PLL0822X_LOCK_STAT_SHIFT (29) +#define PLL0822X_ENABLE_SHIFT (31) + +static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, pll_con3; + u64 fvco = parent_rate; + + pll_con3 = readl_relaxed(pll->con_reg); + mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; + pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; + sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + const struct samsung_pll_rate_table *rate; + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 pll_con3; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, clk_hw_get_name(hw)); + return -EINVAL; + } + + /* Change PLL PMS values */ + pll_con3 = readl_relaxed(pll->con_reg); + pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) | + (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) | + (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT)); + pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) | + (rate->pdiv << PLL0822X_PDIV_SHIFT) | + (rate->sdiv << PLL0822X_SDIV_SHIFT); + + /* Set PLL lock time */ + writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR, + pll->lock_reg); + + /* Write PMS values */ + writel_relaxed(pll_con3, pll->con_reg); + + /* Wait for PLL lock if the PLL is enabled */ + if (pll_con3 & BIT(pll->enable_offs)) + return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); + + return 0; +} + +static const struct clk_ops samsung_pll0822x_clk_ops = { + .recalc_rate = samsung_pll0822x_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll0822x_set_rate, + .enable = samsung_pll3xxx_enable, + .disable = samsung_pll3xxx_disable, +}; + +static const struct clk_ops samsung_pll0822x_clk_min_ops = { + .recalc_rate = samsung_pll0822x_recalc_rate, +}; + /* * PLL45xx Clock Type */ @@ -1296,6 +1379,14 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_pll35xx_clk_ops; break; + case pll_0822x: + pll->enable_offs = PLL0822X_ENABLE_SHIFT; + pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; + if (!pll->rate_table) + init.ops = &samsung_pll0822x_clk_min_ops; + else + init.ops = &samsung_pll0822x_clk_ops; + break; case pll_4500: init.ops = &samsung_pll45xx_clk_min_ops; break; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 79e41c226b90..213e94a97f23 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -36,6 +36,7 @@ enum samsung_pll_type { pll_1451x, pll_1452x, pll_1460x, + pll_0822x, }; #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \