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AJvYcCXzlVmUCXn0zu9k0h8a1OohUL8Xw94XommPVdj7cq+fN6yms3mQCWai4m0AMBdsIaUPCeWqDnQiHtbiRv+pQFDfjFYxWtMrpeCyVYnF7gB4AA0= X-Gm-Message-State: AOJu0YzokO3oo6AAMG86/3EU6uXzaDry3dduGEtFvak92FSXVM+vBBeu IBqTRZZbGjQVbLxkqSgxYiRvBKSIloOVZsOrj1FgiVxZ90Lg1skuiv6T8oP9A7k= X-Google-Smtp-Source: AGHT+IHeX/VVaDgecegUcpaWA/skSWOBVt/xVSoqnnYvRfOPU4y3ogz98bAHizNk9TNynIFmoDyEog== X-Received: by 2002:a5d:6306:0:b0:34c:7410:d6c8 with SMTP id i6-20020a5d6306000000b0034c7410d6c8mr942894wru.49.1714138712119; Fri, 26 Apr 2024 06:38:32 -0700 (PDT) Received: from gpeter-l.lan ([2a0d:3344:2e8:8510:63cc:9bae:f542:50e4]) by smtp.gmail.com with ESMTPSA id p3-20020a5d6383000000b00341b451a31asm22327689wru.36.2024.04.26.06.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 06:38:31 -0700 (PDT) From: Peter Griffin To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, kernel-team@android.com, Peter Griffin Subject: [PATCH v3 2/4] arm64: dts: exynos: gs101: Add the hsi2 sysreg node Date: Fri, 26 Apr 2024 14:38:22 +0100 Message-ID: <20240426133824.2283144-3-peter.griffin@linaro.org> X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog In-Reply-To: <20240426133824.2283144-1-peter.griffin@linaro.org> References: <20240426133824.2283144-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This has some configuration bits such as sharability that are required by UFS. Signed-off-by: Peter Griffin Reviewed-by: André Draszik --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 38ac4fb1397e..09044deede63 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 { clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card"; }; + sysreg_hsi2: syscon@14420000 { + compatible = "google,gs101-hsi2-sysreg", "syscon"; + reg = <0x14420000 0x10000>; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>;