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[35.204.239.8]) by smtp.gmail.com with ESMTPSA id ld4-20020a170906f94400b00a5906d14c31sm1140887ejb.64.2024.04.29.13.04.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 13:04:42 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Mon, 29 Apr 2024 21:04:41 +0100 Subject: [PATCH 4/4] arm64: dts: exynos: gs101: specify placeholder clocks for remaining pinctrl Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240429-samsung-pinctrl-busclock-dts-v1-4-5e935179f3ca@linaro.org> References: <20240429-samsung-pinctrl-busclock-dts-v1-0-5e935179f3ca@linaro.org> In-Reply-To: <20240429-samsung-pinctrl-busclock-dts-v1-0-5e935179f3ca@linaro.org> To: Peter Griffin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Tudor Ambarus , Will McVicker , Sam Protsenko , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andr?= =?utf-8?q?=C3=A9_Draszik?= X-Mailer: b4 0.12.4 The pinctrl instances hsi1, gsactrl, and gsacore need a clock for register access to work. Since we haven't implemented the relevant CMUs for the clocks required by these instances just add placeholder clocks for now so as to make the DT pass the validation checks. Once the clocks are implmented in the gs101 clock driver, these should be updated then. Signed-off-by: André Draszik --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index f8fcbbb06e7b..6db2c9bbb371 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -180,6 +180,14 @@ HERA_CPU_SLEEP: cpu-hera-sleep { }; }; + /* TODO: Remove this once all pinctrl clocks are implemented */ + clk_placeholder: clock-placeholder { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "placeholder_clk"; + }; + /* ect node is required to be present by bootloader */ ect { }; @@ -1309,6 +1317,9 @@ usbdrd31_dwc3: usb@0 { pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; + /* TODO: update once support for this CMU exists */ + clocks = <&clk_placeholder>; + clock-names = "pclk"; interrupts = ; }; @@ -1380,11 +1391,17 @@ wakeup-interrupt-controller { pinctrl_gsactrl: pinctrl@17940000 { compatible = "google,gs101-pinctrl"; reg = <0x17940000 0x00001000>; + /* TODO: update once support for this CMU exists */ + clocks = <&clk_placeholder>; + clock-names = "pclk"; }; pinctrl_gsacore: pinctrl@17a80000 { compatible = "google,gs101-pinctrl"; reg = <0x17a80000 0x00001000>; + /* TODO: update once support for this CMU exists */ + clocks = <&clk_placeholder>; + clock-names = "pclk"; }; cmu_top: clock-controller@1e080000 {