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AJvYcCWgIpS3tSUAyus0AS1zKut3YDGZQi2aN/vo9MjqMXfiH7OSV9vV2zBsdsErsLUQpDmWOCSZGWsSUjLvrrS4vDmqKqNltQBvS7+5YxnMzaCvVsU= X-Gm-Message-State: AOJu0Yx/i/6W/r5+RjLk1GtqdZ03lcCVhI/H2SlBjISlBTTSd8OyZIIB VHvG5KoMouJyZvN2y9z7uMnOW+30rUoVfok1Dh6IJq+P8wlfXAwifuEoqA9uvIQ= X-Google-Smtp-Source: AGHT+IFOV6Boiua6vxtgJwU/ckgGydalUeT2SdoUtWSqR0XQEJrQaX1crPbKpSVki5bjWuWmiiGApQ== X-Received: by 2002:a05:600c:1988:b0:418:f826:58c3 with SMTP id t8-20020a05600c198800b00418f82658c3mr11554553wmq.15.1714486492681; Tue, 30 Apr 2024 07:14:52 -0700 (PDT) Received: from gpeter-l.lan ([2a0d:3344:2e8:8510:f162:7aca:a805:2c2f]) by smtp.gmail.com with ESMTPSA id r10-20020a05600c458a00b0041bf3a716b9sm11593517wmo.34.2024.04.30.07.14.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 07:14:52 -0700 (PDT) From: Peter Griffin To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, kernel-team@android.com, Peter Griffin Subject: [PATCH v5 1/3] arm64: dts: exynos: gs101: Add the hsi2 sysreg node Date: Tue, 30 Apr 2024 15:14:43 +0100 Message-ID: <20240430141445.2688499-2-peter.griffin@linaro.org> X-Mailer: git-send-email 2.45.0.rc0.197.gbae5840b3b-goog In-Reply-To: <20240430141445.2688499-1-peter.griffin@linaro.org> References: <20240430141445.2688499-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This has some configuration bits such as sharability that are required by UFS. Signed-off-by: Peter Griffin Reviewed-by: André Draszik --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index e3b068c1a2c1..9f7635a7928e 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1320,6 +1320,12 @@ cmu_hsi2: clock-controller@14400000 { clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; }; + sysreg_hsi2: syscon@14420000 { + compatible = "google,gs101-hsi2-sysreg", "syscon"; + reg = <0x14420000 0x10000>; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>;