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[37.248.155.75]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a79bc7ff888sm351179866b.159.2024.07.16.12.36.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 12:36:16 -0700 (PDT) From: Artur Weber Date: Tue, 16 Jul 2024 21:36:08 +0200 Subject: [PATCH 4/6] ARM: dts: samsung: exynos4212-tab3: Add MCLK2 clock to WM1811 codec config Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240716-midas-audio-tab3-v1-4-a53ea075af5a@gmail.com> References: <20240716-midas-audio-tab3-v1-0-a53ea075af5a@gmail.com> In-Reply-To: <20240716-midas-audio-tab3-v1-0-a53ea075af5a@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1158; i=aweber.kernel@gmail.com; h=from:subject:message-id; bh=QgWGYzqvHsjqfBL4j0SgJZ5JxQSnDNVwolJTCMyITN8=; b=owEBbQKS/ZANAwAKAbO7+KEToFFoAcsmYgBmlsunUETQ1dVc8FKwNP4+eeUj5fugkIRozC1vV igRSF+i0/KJAjMEAAEKAB0WIQTmYwAOrB3szWrSiQ2zu/ihE6BRaAUCZpbLpwAKCRCzu/ihE6BR aMP7D/0WPdFsO2koC9szvz/Srxq22hpYb8obGNYBICHfaV95VXvIUO7yej2P93XYB6MyxN4+xPv 0tRGWFVpkZfnVY6ya1VyZGlnBHdFiEDIngTXio9DiR2quosMa+fpZ8m+NCPGZfQiOUwc6RcALMD uARnkFNwfaO4jfWFV46MLO4kTheAz1ga/CMnE+MnqFZt/9eH+qasHV4cvLkmszVmTlbm0xXLfVC 4/rJRgwcgv/VfMVGIZRp3zjrpTOwU0E8MTBGRvilVAuOcqk2IVg7bps29g0Sgo0MpH2rpA4Vjaz hiXpyqa8S8omd+j6s8AEHsuqbQu3J7UwaaYqvu8KRqV2PpsfeRgASmOwbSXAcvwk4T6Ed7RbwX8 8bcRmA1WzI1IDGoxq82oayH4fp5BSROkEuN38qWinFqkvkY0F0H90yrrNacEYQSof2bkNiqu26/ n/G3CbrpYAtbdBeXIBtBQEm/+E2QcVnjf95e0YAKzKU+O5vojLWZ8n0qCyPwDgCuGGPYY1igV6S H0QRrkusT7PUBfukJlwZi1cXsTK3LR+o/cpJQkWg/EfMmH01pKmYunXh03/RmeSytGnPTzIZnD0 D3nFoU4mv3wnKQH+jpreCQ5cEJchKxtjOtKllQ0LnSlKqB27Wrx44mhJ/rZHtG1lC4V+shrn5QB EhTXzlmz3ie6uVg== X-Developer-Key: i=aweber.kernel@gmail.com; a=openpgp; fpr=E663000EAC1DECCD6AD2890DB3BBF8A113A05168 In the schematics, the MCLK2 pin is shown as connected to CODEC_CLK32K, which is derived from the same 32KHZ_PMIC clock as Bluetooth/WiFi and GPS clocks. 32KHZ_PMIC is connected to the BTCLK pin, represented in mainline as S2MPS11_CLK_BT. Add the MCLK2 clock to the WM1811 codec clock property to properly describe the hardware. Signed-off-by: Artur Weber --- arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi index 45003967406a..46bdd0681afe 100644 --- a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi @@ -535,8 +535,9 @@ &i2c_4 { wm1811: audio-codec@1a { compatible = "wlf,wm1811"; reg = <0x1a>; - clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; + clocks = <&pmu_system_controller 0>, + <&s5m8767_osc S2MPS11_CLK_BT>; + clock-names = "MCLK1", "MCLK2"; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&gpx3>;