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AJvYcCVWqVLafDbeZLmB9AJjf2oJhYS8zQxMMePXheJTK/IeaeQ8LMJXerPm68VonjEMKkM14GqHoBiaTps0p2Ok70CHp0TURnYP7WLwaE+FxSRkTUEyJ3uVO8540QSbVa9FiPGst88oAu2+CR3MLjiG5891FIxEjdsGb4/i2/YiQpyBW1fi8g== X-Gm-Message-State: AOJu0YzWiTJzReYJ5xr/HLlC1FjCSyB81I7/vOogVGkEm7eLhAy9iDzu BJDdAuEmws1pbmJkKS6eMFT7WAKql4s68S0EGpO+aBgAiJ92WfI/5miTVVnm X-Google-Smtp-Source: AGHT+IER7UQAupfaALkh21KXTUHksXS5mAGOEgSKzg1JMEgFGXs1o1YHpIeUETH6wcVoq+6kQFDQIQ== X-Received: by 2002:a17:907:2d89:b0:a7d:c9fa:e3b3 with SMTP id a640c23a62f3a-a7dc9faeb5fmr1086181066b.54.1722946293025; Tue, 06 Aug 2024 05:11:33 -0700 (PDT) Received: from localhost.localdomain ([2a02:ab88:3711:c80:e7a7:e025:f1a5:ef78]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-a7dc9ecb546sm542080366b.224.2024.08.06.05.11.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Aug 2024 05:11:32 -0700 (PDT) From: David Virag To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , David Virag Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/7] dt-bindings: clock: exynos7885: Add indices for USB clocks Date: Tue, 6 Aug 2024 14:11:46 +0200 Message-ID: <20240806121157.479212-4-virag.david003@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240806121157.479212-1-virag.david003@gmail.com> References: <20240806121157.479212-1-virag.david003@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Exynos7885 SoC has a DWC3 USB Controller with Exynos USB PHY which in theory supports USB3 SuperSpeed, but is only used as USB2 in all known devices. These, of course, need some clocks. Add indices for these clocks. Signed-off-by: David Virag --- include/dt-bindings/clock/exynos7885.h | 30 ++++++++++++++++---------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h index 4ce86810b10d..cfede84b46b9 100644 --- a/include/dt-bindings/clock/exynos7885.h +++ b/include/dt-bindings/clock/exynos7885.h @@ -134,16 +134,24 @@ #define CLK_GOUT_WDT1_PCLK 43 /* CMU_FSYS */ -#define CLK_MOUT_FSYS_BUS_USER 1 -#define CLK_MOUT_FSYS_MMC_CARD_USER 2 -#define CLK_MOUT_FSYS_MMC_EMBD_USER 3 -#define CLK_MOUT_FSYS_MMC_SDIO_USER 4 -#define CLK_GOUT_MMC_CARD_ACLK 5 -#define CLK_GOUT_MMC_CARD_SDCLKIN 6 -#define CLK_GOUT_MMC_EMBD_ACLK 7 -#define CLK_GOUT_MMC_EMBD_SDCLKIN 8 -#define CLK_GOUT_MMC_SDIO_ACLK 9 -#define CLK_GOUT_MMC_SDIO_SDCLKIN 10 -#define CLK_MOUT_FSYS_USB30DRD_USER 11 +#define CLK_MOUT_FSYS_BUS_USER 1 +#define CLK_MOUT_FSYS_MMC_CARD_USER 2 +#define CLK_MOUT_FSYS_MMC_EMBD_USER 3 +#define CLK_MOUT_FSYS_MMC_SDIO_USER 4 +#define CLK_GOUT_MMC_CARD_ACLK 5 +#define CLK_GOUT_MMC_CARD_SDCLKIN 6 +#define CLK_GOUT_MMC_EMBD_ACLK 7 +#define CLK_GOUT_MMC_EMBD_SDCLKIN 8 +#define CLK_GOUT_MMC_SDIO_ACLK 9 +#define CLK_GOUT_MMC_SDIO_SDCLKIN 10 +#define CLK_MOUT_FSYS_USB30DRD_USER 11 +#define CLK_MOUT_USB_PLL 12 +#define CLK_FOUT_USB_PLL 13 +#define CLK_FSYS_USB20PHY_CLKCORE 14 +#define CLK_FSYS_USB30DRD_ACLK_20PHYCTRL 15 +#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0 16 +#define CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1 17 +#define CLK_FSYS_USB30DRD_BUS_CLK_EARLY 18 +#define CLK_FSYS_USB30DRD_REF_CLK 19 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */