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Mon, 19 Aug 2024 07:55:46 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20240819075546epsmtrp183c4ee2adb89210c9ef1fda81d97c672~tEhyRXFQA0521805218epsmtrp1j; Mon, 19 Aug 2024 07:55:46 +0000 (GMT) X-AuditID: b6c32a33-96dfa70000002320-20-66c2fa82e119 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 35.21.08964.28AF2C66; Mon, 19 Aug 2024 16:55:46 +0900 (KST) Received: from [127.0.1.1] (unknown [10.113.111.204]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20240819075546epsmtip25b31c4fc2d63e23398132ff3af59e6ce~tEhyE9Pmc2794427944epsmtip2X; Mon, 19 Aug 2024 07:55:46 +0000 (GMT) From: Kwanghoon Son Date: Mon, 19 Aug 2024 16:55:45 +0900 Subject: [PATCH] arm64: dts: exynosautov9: Add dpum SysMMU Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240819-add_sysmmu-v1-1-799c0f3f607f@samsung.com> X-B4-Tracking: v=1; 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This sysmmu is version 7.4, which has same functionality as exynos850. DPUM has 4 dma channel, each channel is mapped to one iommu. Signed-off-by: Kwanghoon Son --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) --- base-commit: 367b5c3d53e57d51a5878816804652963da90950 change-id: 20240819-add_sysmmu-1a89611ddee4 Best regards, diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 599e72824875..b36292a7db64 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -261,6 +261,42 @@ cmu_dpum: clock-controller@18c00000 { clock-names = "oscclk", "bus"; }; + sysmmu_dpum_0: sysmmu@18c80000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x18c80000 0x10000>; + interrupts = ; + clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D0_CLK>; + clock-names = "sysmmu"; + #iommu-cells = <0>; + }; + + sysmmu_dpum_1: sysmmu@18c90000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x18c90000 0x10000>; + interrupts = ; + clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D1_CLK>; + clock-names = "sysmmu"; + #iommu-cells = <0>; + }; + + sysmmu_dpum_2: sysmmu@18ca0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x18ca0000 0x10000>; + interrupts = ; + clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D2_CLK>; + clock-names = "sysmmu"; + #iommu-cells = <0>; + }; + + sysmmu_dpum_3: sysmmu@18cb0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x18cb0000 0x10000>; + interrupts = ; + clocks = <&cmu_dpum CLK_GOUT_DPUM_SYSMMU_D3_CLK>; + clock-names = "sysmmu"; + #iommu-cells = <0>; + }; + cmu_core: clock-controller@1b030000 { compatible = "samsung,exynosautov9-cmu-core"; reg = <0x1b030000 0x8000>;