From patchwork Thu Sep 19 15:11:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaustabh Chakraborty X-Patchwork-Id: 829795 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4710A1A3BD9; Thu, 19 Sep 2024 15:11:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726758926; cv=none; b=QVaBIubnNVjDDB5M9FjHjQUo6o+Ma51lL9Z7LocFBtsIKDwQKGBWbSXNFzEoowCvHV5NvI87QFStnaZ7HsKgmt0JovzpNAvq1/CbaWCuBprzIMV36xcXde8CriVweGQhS20Nl7sLFZahxAQmZkj/slISM2rD7g8Dn9HHaARsmPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726758926; c=relaxed/simple; bh=8o85bus/0rE9Cesf9JRpcxZtGUE4BpUrbgAzVXQTVc8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Fof8BiYcQXDT+4d6IU9WjL9ESr7oS1ONULb3yK0UvWncbWzG6cLWTSBZTgcHrkNAa/nSfKOGdlyxdqCoLGJlF3Dgcg/NMRR5jMRH81Lwby/Lpa3+90KQ49qSdYvIjotcA8NlAWriadOjVo6txUnHlmq6CIbLubM/JbfpdlH4EDw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=Ysj/aRL1; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="Ysj/aRL1" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id CF3BA23DFD; Thu, 19 Sep 2024 17:11:48 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id n1VxGGLcqtJu; Thu, 19 Sep 2024 17:11:48 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1726758708; bh=8o85bus/0rE9Cesf9JRpcxZtGUE4BpUrbgAzVXQTVc8=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Ysj/aRL1u62Gn0awDl+2XPfKVS13f8EXYghIEeMliIlwn5jzVVvdCuysWvDE+uQCQ 67/TQICD+TqkPLwscbpSQg1zSyi1QUq0Zzk3JnCnQfLQLz983c9WTdI7Y0XepMi8mq hoPzjWXqpQTFTUgf8sERtWD5OZs8tzk/cGvA//Wj1w+f8DO2dUDjs/1sKxWQFKgPu/ U8lWt06vJ+kLzq7EEHCM3hvDPmopftnN9hR/NBPDmXSUi/S7IT49y1+GF1uVbTetJA UT8twdv64OwFRzTwLWyN9zw6AtywymqtajFXrv/dwauDFXgTCEu6OCb05LSH2YAPWH iaWxXRetkRTGA== From: Kaustabh Chakraborty Date: Thu, 19 Sep 2024 20:41:03 +0530 Subject: [PATCH 4/6] drm/exynos: exynos7_drm_decon: properly clear channels during bind Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240919-exynosdrm-decon-v1-4-6c5861c1cb04@disroot.org> References: <20240919-exynosdrm-decon-v1-0-6c5861c1cb04@disroot.org> In-Reply-To: <20240919-exynosdrm-decon-v1-0-6c5861c1cb04@disroot.org> To: Inki Dae , Seung-Woo Kim , Kyungmin Park , David Airlie , Simona Vetter , Krzysztof Kozlowski , Alim Akhtar , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Conor Dooley Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Kaustabh Chakraborty The DECON channels are not cleared properly as the windows aren't shadow protected. When accompanied with an IOMMU, it pagefaults, and the kernel panics. Implement shadow protect/unprotect, along with a standalone update, for channel clearing to properly take effect. Signed-off-by: Kaustabh Chakraborty --- drivers/gpu/drm/exynos/exynos7_drm_decon.c | 55 +++++++++++++++++------------- 1 file changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index 4e4ced50ff15..7f0985eb216e 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -81,6 +81,28 @@ static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { DRM_PLANE_TYPE_CURSOR, }; +/** + * decon_shadow_protect_win() - disable updating values from shadow registers at vsync + * + * @ctx: display and enhancement controller context + * @win: window to protect registers for + * @protect: 1 to protect (disable updates) + */ +static void decon_shadow_protect_win(struct decon_context *ctx, + unsigned int win, bool protect) +{ + u32 bits, val; + + bits = SHADOWCON_WINx_PROTECT(win); + + val = readl(ctx->regs + SHADOWCON); + if (protect) + val |= bits; + else + val &= ~bits; + writel(val, ctx->regs + SHADOWCON); +} + static void decon_wait_for_vblank(struct decon_context *ctx) { if (ctx->suspended) @@ -101,18 +123,27 @@ static void decon_wait_for_vblank(struct decon_context *ctx) static void decon_clear_channels(struct decon_context *ctx) { unsigned int win, ch_enabled = 0; + u32 val; /* Check if any channel is enabled. */ for (win = 0; win < WINDOWS_NR; win++) { - u32 val = readl(ctx->regs + WINCON(win)); + val = readl(ctx->regs + WINCON(win)); if (val & WINCONx_ENWIN) { + decon_shadow_protect_win(ctx, win, true); + val &= ~WINCONx_ENWIN; writel(val, ctx->regs + WINCON(win)); ch_enabled = 1; + + decon_shadow_protect_win(ctx, win, false); } } + val = readl(ctx->regs + DECON_UPDATE); + val |= DECON_UPDATE_STANDALONE_F; + writel(val, ctx->regs + DECON_UPDATE); + /* Wait for vsync, as disable channel takes effect at next vsync */ if (ch_enabled) decon_wait_for_vblank(ctx); @@ -340,28 +371,6 @@ static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); } -/** - * decon_shadow_protect_win() - disable updating values from shadow registers at vsync - * - * @ctx: display and enhancement controller context - * @win: window to protect registers for - * @protect: 1 to protect (disable updates) - */ -static void decon_shadow_protect_win(struct decon_context *ctx, - unsigned int win, bool protect) -{ - u32 bits, val; - - bits = SHADOWCON_WINx_PROTECT(win); - - val = readl(ctx->regs + SHADOWCON); - if (protect) - val |= bits; - else - val &= ~bits; - writel(val, ctx->regs + SHADOWCON); -} - static void decon_atomic_begin(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx;