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AJvYcCV/E7QQ7t0Z4g/X7YTzk5G1aoPxTMXq0IoSUK381XuiyOeGAot06K3oOGxELyhr1uk4iiVKxGmxQImPhHW23MDdpA==@vger.kernel.org X-Gm-Message-State: AOJu0Yy26VLAZj1pmrfjhw0yxKOcX+X57wM2t6gvr3HaAMlQXAO2YoKX Fc5GM8CusFMGKM5ISeyaqe2WOYCYDAj9CQ+tdLJ03gOjF2V2v3LMZ8IbsP9AeF0= X-Google-Smtp-Source: AGHT+IGBloKnQyzK042bxpPzzNwKfFJqeBubjE+dIc7DcjDnTJukogo204p6ptQH0HImb9KtmNPitA== X-Received: by 2002:a05:600c:1d1c:b0:431:55bf:fe4 with SMTP id 5b1f17b1804b1-431b17365ffmr107037035e9.24.1730386850219; Thu, 31 Oct 2024 08:00:50 -0700 (PDT) Received: from gpeter-l.lan ([145.224.65.232]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd8e8524sm59163225e9.5.2024.10.31.08.00.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Oct 2024 08:00:49 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: tudor.ambarus@linaro.org, ebiggers@kernel.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Griffin Subject: [PATCH v3 10/14] scsi: ufs: exynos: enable write line unique transactions on gs101 Date: Thu, 31 Oct 2024 15:00:29 +0000 Message-ID: <20241031150033.3440894-11-peter.griffin@linaro.org> X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog In-Reply-To: <20241031150033.3440894-1-peter.griffin@linaro.org> References: <20241031150033.3440894-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently just AXIDMA_RWDATA_BURST_LEN[3:0] field is set to 8 in exynos_ufs_post_link() function. To enable WLU transaction additionally we need to set Write Line Unique enable [31], Write Line Unique Burst Length [30:27] and AXIDMA_RWDATA_BURST_LEN[3:0]. To support WLU transaction on gs101, both burst length fields need to be 0x3. As all other SoCs expect the current value we update this in the gs101_ufs_post_link() specific hook. Signed-off-by: Peter Griffin Reviewed-by: Tudor Ambarus --- v3: fix typo s/burth/burst typo (Tudor) v3: update commit message (Peter) --- drivers/ufs/host/ufs-exynos.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index d59e1933b64e..78307440107f 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -48,6 +48,8 @@ #define HCI_UNIPRO_APB_CLK_CTRL 0x68 #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF)) #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C +#define WLU_EN BIT(31) +#define WLU_BURST_LEN(x) ((x) << 27 | ((x) & 0xF)) #define HCI_GPIO_OUT 0x70 #define HCI_ERR_EN_PA_LAYER 0x78 #define HCI_ERR_EN_DL_LAYER 0x7C @@ -1922,6 +1924,12 @@ static int gs101_ufs_post_link(struct exynos_ufs *ufs) { struct ufs_hba *hba = ufs->hba; + /* + * Enable Write Line Unique. This field has to be 0x3 + * to support Write Line Unique transaction on gs101. + */ + hci_writel(ufs, WLU_EN | WLU_BURST_LEN(3), HCI_AXIDMA_RWDATA_BURST_LEN); + exynos_ufs_enable_dbg_mode(hba); ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8); exynos_ufs_disable_dbg_mode(hba);