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Mon, 28 Apr 2025 08:47:28 +0000 (GMT) Received: from epsmgmcp1.samsung.com (unknown [182.195.42.82]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20250428084728epsmtrp174d195cdaba526ea41263bb1f6542b04~6by3rh5KQ2986529865epsmtrp1Y; Mon, 28 Apr 2025 08:47:28 +0000 (GMT) X-AuditID: b6c32a52-40bff70000004c16-cc-680f40a03307 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgmcp1.samsung.com (Symantec Messaging Gateway) with SMTP id E2.CF.19478.0A04F086; Mon, 28 Apr 2025 17:47:28 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.60]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250428084728epsmtip141d3738578162e2eca70d97b76378d1b~6by3bPxOp1942219422epsmtip1G; Mon, 28 Apr 2025 08:47:28 +0000 (GMT) From: Shin Son To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Sunyeal Hong Cc: Shin Son , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions Date: Mon, 28 Apr 2025 17:47:19 +0900 Message-ID: <20250428084721.3832664-2-shin.son@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428084721.3832664-1-shin.son@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOLMWRmVeSWpSXmKPExsWy7bCSnO4CB/4Mg/uTpC0ezNvGZrFm7zkm i+tfnrNazD9yjtXi/PkN7BabHl9jtfjYc4/V4vKuOWwWM87vY7K4eMrV4v+eHewWh9+0s1r8 u7aRxWLy8bWsFk3L1jM58Hu8v9HK7rFpVSebx+Yl9R59W1YxenzeJBfAGsVlk5Kak1mWWqRv l8CV8e7RG/aC87IVjZe2sjYwHhLrYuTkkBAwkej+sJi5i5GLQ0hgO6NEY8djJoiEhMThGRMY IWxhifstR1ghit4zStyb3sfexcjBwSagKrHptzxIXETgLZPE8v8HwJqZBU4zSuw8IwNiCwuE S3y+f4MZxGYBqb+4jwXE5hWwlmibdoUNZI6EgLxEf4cESJhTwEbi/MVOsLAQUElfDzdEtaDE yZlPWCCmy0s0b53NPIFRYBaS1CwkqQWMTKsYRVMLinPTc5MLDPWKE3OLS/PS9ZLzczcxguNC K2gH47L1f/UOMTJxMB5ilOBgVhLhrTLgzxDiTUmsrEotyo8vKs1JLT7EKM3BoiTOq5zTmSIk kJ5YkpqdmlqQWgSTZeLglGpgCosTW+DWcrw1YPqBMzXrSmRy+f6lx9yXm7xUZ3PnR2eD20ob 7k7+9uDF2wWSn1RnqbvtTzVqYtnsUvrtZNWsvU917Ex9LM7f+XtGwXnhrxue4VvesavvKnkp 3vBe9bfc4nvLLlz4WHqt/C7DXL+jAk991L/HLsxVuiDv43NjTdlGnym+m18t15HRUZrfk67T 9f+/VOOpTPmiq+fEX5puenKw97pwQ6beWcWSw3vrXs2NPFHHW9i34tGvKX7hV34fzMiwFK1i t/h6vOSksWPWHhWh4uvPln6ZxrpRRm9v28btr2S6+PPz7BeE5fy/FHVnn8uD4g/OH7av+tC3 dt+DbRyXNi+LWfosVPrPxSTdCa+VWIozEg21mIuKEwHlZRX5+gIAAA== X-CMS-MailID: 20250428084728epcas2p34ffa0051a16c10ff1c358a98cc2c2fa4 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250428084728epcas2p34ffa0051a16c10ff1c358a98cc2c2fa4 References: <20250428084721.3832664-1-shin.son@samsung.com> Add cpucl1 and cpucl2 clock definitions. CPUCL1/2 refer to CPU Cluster 1 and CPU Cluster 2, which provide clock support for the CPUs on Exynosauto V920 SoC. Signed-off-by: Shin Son --- .../clock/samsung,exynosautov920-clock.yaml | 45 +++++++++++++++++++ .../clock/samsung,exynosautov920.h | 32 +++++++++++++ 2 files changed, 77 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml index d12b17c177df..dbeae0cb0cb9 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml @@ -34,6 +34,8 @@ properties: enum: - samsung,exynosautov920-cmu-top - samsung,exynosautov920-cmu-cpucl0 + - samsung,exynosautov920-cmu-cpucl1 + - samsung,exynosautov920-cmu-cpucl2 - samsung,exynosautov920-cmu-peric0 - samsung,exynosautov920-cmu-peric1 - samsung,exynosautov920-cmu-misc @@ -94,6 +96,49 @@ allOf: - const: cluster - const: dbg + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl1 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL1 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl2 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL2 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h index c57a1d749700..5e6896e9627f 100644 --- a/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/include/dt-bindings/clock/samsung,exynosautov920.h @@ -181,6 +181,38 @@ #define CLK_DOUT_CPUCL0_DBG_PCLKDBG 14 #define CLK_DOUT_CPUCL0_NOCP 15 +/* CMU_CPUCL1 */ +#define CLK_FOUT_CPUCL1_PLL 1 + +#define CLK_MOUT_PLL_CPUCL1 2 +#define CLK_MOUT_CPUCL1_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL1_SWITCH_USER 4 +#define CLK_MOUT_CPUCL1_CLUSTER 5 +#define CLK_MOUT_CPUCL1_CORE 6 + +#define CLK_DOUT_CLUSTER1_ACLK 7 +#define CLK_DOUT_CLUSTER1_ATCLK 8 +#define CLK_DOUT_CLUSTER1_MPCLK 9 +#define CLK_DOUT_CLUSTER1_PCLK 10 +#define CLK_DOUT_CLUSTER1_PERIPHCLK 11 +#define CLK_DOUT_CPUCL1_NOCP 12 + +/* CMU_CPUCL2 */ +#define CLK_FOUT_CPUCL2_PLL 1 + +#define CLK_MOUT_PLL_CPUCL2 2 +#define CLK_MOUT_CPUCL2_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL2_SWITCH_USER 4 +#define CLK_MOUT_CPUCL2_CLUSTER 5 +#define CLK_MOUT_CPUCL2_CORE 6 + +#define CLK_DOUT_CLUSTER2_ACLK 7 +#define CLK_DOUT_CLUSTER2_ATCLK 8 +#define CLK_DOUT_CLUSTER2_MPCLK 9 +#define CLK_DOUT_CLUSTER2_PCLK 10 +#define CLK_DOUT_CLUSTER2_PERIPHCLK 11 +#define CLK_DOUT_CPUCL2_NOCP 12 + /* CMU_PERIC0 */ #define CLK_MOUT_PERIC0_IP_USER 1 #define CLK_MOUT_PERIC0_NOC_USER 2