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Mon, 28 Apr 2025 11:35:47 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20250428113547epsmtrp2503eb2c944376df9ca94915b20cc0f89~6eF1GisHo1223712237epsmtrp2c; Mon, 28 Apr 2025 11:35:47 +0000 (GMT) X-AuditID: b6c32a29-566fe7000000223e-c7-680f6813a178 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 52.F1.08766.3186F086; Mon, 28 Apr 2025 20:35:47 +0900 (KST) Received: from localhost.localdomain (unknown [10.229.9.60]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250428113547epsmtip19926f82ffb5b3521533d66fbd4879c55~6eF06pstP2476824768epsmtip1b; Mon, 28 Apr 2025 11:35:47 +0000 (GMT) From: Shin Son To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Sunyeal Hong Cc: Shin Son , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/4] dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions Date: Mon, 28 Apr 2025 20:35:14 +0900 Message-ID: <20250428113517.426987-2-shin.son@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428113517.426987-1-shin.son@samsung.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrFLMWRmVeSWpSXmKPExsWy7bCSnK5wBn+GQc9peYsH87axWazZe47J 4vqX56wW84+cY7U4f34Du8Wmx9dYLT723GO1uLxrDpvFjPP7mCwunnK1+L9nB7vF4TftrBb/ rm1ksZh8fC2rRdOy9UwO/B7vb7Sye2xa1cnmsXlJvUffllWMHp83yQWwRnHZpKTmZJalFunb JXBlbL33l6XgrGzF4uU/2BoYD4l1MXJySAiYSHzrf8rcxcjFISSwm1Fibt9EZoiEhMThGRMY IWxhifstR1ghit4zSjxY/o29i5GDg01AVWLTb3mQuIjAWyaJ5f8PMIE0MAucZpTYeUYGxBYW iJJobt/ADFLPAlR/uC8exOQVsJK4P1UIxJQQkJfo75AAKeYUsJb4dHEd2AVCQBUTHp9hA7F5 BQQlTs58wgIxXF6ieets5gmMArOQpGYhSS1gZFrFKJlaUJybnltsWGCYl1quV5yYW1yal66X nJ+7iREcHVqaOxi3r/qgd4iRiYPxEKMEB7OSCG+VAX+GEG9KYmVValF+fFFpTmrxIUZpDhYl cV7xF70pQgLpiSWp2ampBalFMFkmDk6pBqaIJXK7Atw5n79iU7tVYVV88alyGkdAxnv731Pa zvIxeH/zdxddvnOq2O8LXxZpvs5/K+rgrjd/f8QO5um99118vwgLyejInfDQbmh9lzD1ku/E P6WxFRbzlfO454mzFzq48MWZ5x5aznzI177//VTLT6InGPLsdD/92i5iUWXSlFbyLr3kUis3 75uIS59E9ogtKk/X4A7LXMmSPr3tcVoCX6NE7T6HY19Kn914fn71ig/bGsLj3DeX3D974HeZ gf9TnwvP8riCvp//wq59w2i2UR3ftbB9chOS1ENV+1ZI+Jsev7rKO68jXXb/hqLLLx7+W/wq tfPVR4+SW5FFwlIl8iGbvi8t8yvvjxOfocRSnJFoqMVcVJwIAMEGOWT9AgAA X-CMS-MailID: 20250428113547epcas2p43ca3c8db840a4235365f61151b043fb3 X-Msg-Generator: CA X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250428113547epcas2p43ca3c8db840a4235365f61151b043fb3 References: <20250428113517.426987-1-shin.son@samsung.com> Add cpucl1 and cpucl2 clock definitions. CPUCL1/2 refer to CPU Cluster 1 and CPU Cluster 2, which provide clock support for the CPUs on Exynosauto V920 SoC. Signed-off-by: Shin Son --- .../clock/samsung,exynosautov920-clock.yaml | 44 +++++++++++++++++++ .../clock/samsung,exynosautov920.h | 32 ++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml index d12b17c177df..6961a68098f4 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml @@ -34,6 +34,8 @@ properties: enum: - samsung,exynosautov920-cmu-top - samsung,exynosautov920-cmu-cpucl0 + - samsung,exynosautov920-cmu-cpucl1 + - samsung,exynosautov920-cmu-cpucl2 - samsung,exynosautov920-cmu-peric0 - samsung,exynosautov920-cmu-peric1 - samsung,exynosautov920-cmu-misc @@ -94,6 +96,48 @@ allOf: - const: cluster - const: dbg + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl1 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL1 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-cmu-cpucl2 + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_CPUCL2 SWITCH clock (from CMU_TOP) + - description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: switch + - const: cluster + - if: properties: compatible: diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h index c57a1d749700..5e6896e9627f 100644 --- a/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/include/dt-bindings/clock/samsung,exynosautov920.h @@ -181,6 +181,38 @@ #define CLK_DOUT_CPUCL0_DBG_PCLKDBG 14 #define CLK_DOUT_CPUCL0_NOCP 15 +/* CMU_CPUCL1 */ +#define CLK_FOUT_CPUCL1_PLL 1 + +#define CLK_MOUT_PLL_CPUCL1 2 +#define CLK_MOUT_CPUCL1_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL1_SWITCH_USER 4 +#define CLK_MOUT_CPUCL1_CLUSTER 5 +#define CLK_MOUT_CPUCL1_CORE 6 + +#define CLK_DOUT_CLUSTER1_ACLK 7 +#define CLK_DOUT_CLUSTER1_ATCLK 8 +#define CLK_DOUT_CLUSTER1_MPCLK 9 +#define CLK_DOUT_CLUSTER1_PCLK 10 +#define CLK_DOUT_CLUSTER1_PERIPHCLK 11 +#define CLK_DOUT_CPUCL1_NOCP 12 + +/* CMU_CPUCL2 */ +#define CLK_FOUT_CPUCL2_PLL 1 + +#define CLK_MOUT_PLL_CPUCL2 2 +#define CLK_MOUT_CPUCL2_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL2_SWITCH_USER 4 +#define CLK_MOUT_CPUCL2_CLUSTER 5 +#define CLK_MOUT_CPUCL2_CORE 6 + +#define CLK_DOUT_CLUSTER2_ACLK 7 +#define CLK_DOUT_CLUSTER2_ATCLK 8 +#define CLK_DOUT_CLUSTER2_MPCLK 9 +#define CLK_DOUT_CLUSTER2_PCLK 10 +#define CLK_DOUT_CLUSTER2_PERIPHCLK 11 +#define CLK_DOUT_CPUCL2_NOCP 12 + /* CMU_PERIC0 */ #define CLK_MOUT_PERIC0_IP_USER 1 #define CLK_MOUT_PERIC0_NOC_USER 2