From patchwork Thu Feb 28 14:51:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 159382 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp731576jad; Thu, 28 Feb 2019 06:51:50 -0800 (PST) X-Google-Smtp-Source: AHgI3Ib/iELOAmZ1aVzIAtLdBTEAcvm5XkJSQugkX3/IxM1iuh4ZAsM6qA85SEisetum3HizXga6 X-Received: by 2002:a17:902:207:: with SMTP id 7mr8242551plc.142.1551365510501; Thu, 28 Feb 2019 06:51:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551365510; cv=none; d=google.com; s=arc-20160816; b=MF70AV59qeKOWDnFi8CuJvBma73pdy3Yfd02L0Hl1m1voIpXFNWrUWCZ5Sb/LVH3P0 YYWkY1mW+qa/ysRpAIweupl48qE50SxxyCBkkaAujRo7X/sLR2odz8jvFnwVEFVtTgPX 8tWPwY2TDilykz3lTR394ZXaq9pAPlfdBMarx7wxZ9XM4/WcnB4a2bud5Fs528Tjzpj6 oBUWxN1EK2tkkvvDetg79Llx2xbW0sPwzOYCZlHA03BNpU4x9Nclx1jf2NFjNXLFw5Wo 09XcdWiRHsvvyEpbWpqnjjBICVEovypGA2QOVy5hk3c0SHfpDEO8LWs9qrE/bFUGB6O+ W8gQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=QUIvVyAt4IKXJVf98rAhHOYVhlgmgEvSV/rPRAesRkQ=; b=j75sfhWST/VQKXub4gQo67AHOeifY7YAdEmJmZ1lhzWUZBKt3KakCWejtRIzScsLzb 5uQxLpQXnHitya6xAoLV9Pi+JZ0YVmyqL/Wi+DhQ/nKpYwsKTHMfM4fa2JnNshhBv1FK NvJogDxgMnF0osLzf0k2IjWb9IsgCU+CiPqbCSQlQ3vgJnvxjUbuhW+6UfCc/15r1/vk mAWOLEvqnp0FmxqdjdLhMU6rE17TYtpyinl3eALiYWV0MSBq/BXk8Vb3HEan3A83knGT W/L6Z3WxfzRR4v8E4xWHZrCtZH+d7wj8Ga7g6zALcRJ/0n8pxApsoYZSwK2BygZ12GRB ngFg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d7si18692130pgb.116.2019.02.28.06.51.50; Thu, 28 Feb 2019 06:51:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733203AbfB1Ovl (ORCPT + 1 other); Thu, 28 Feb 2019 09:51:41 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:4745 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1733178AbfB1Ovg (ORCPT ); Thu, 28 Feb 2019 09:51:36 -0500 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B22FBD312F0EDEA25D42; Thu, 28 Feb 2019 22:51:30 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.408.0; Thu, 28 Feb 2019 22:51:20 +0800 From: John Garry To: , CC: , , , Xiang Chen , "John Garry" Subject: [PATCH 6/6] scsi: hisi_sas: Change SERDES_CFG init value to increase reliability of HiLink Date: Thu, 28 Feb 2019 22:51:02 +0800 Message-ID: <1551365462-128193-7-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1551365462-128193-1-git-send-email-john.garry@huawei.com> References: <1551365462-128193-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiang Chen With default value of register SERDES_CFG, the link is not stable for some special disks when running IO. According to HW guys' suggestion, need to make the bit10~19 value of register SERDES_CFG the max value to increase the reliability of the HiLink. Signed-off-by: Xiang Chen Reviewed-by: Yupeng Zhou Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 720721196b12..e2f2c04355b9 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -129,6 +129,7 @@ #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) #define CMD_HDR_PIR_OFF 8 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) +#define SERDES_CFG (PORT_BASE + 0x1c) #define SL_CFG (PORT_BASE + 0x84) #define AIP_LIMIT (PORT_BASE + 0x90) #define SL_CONTROL (PORT_BASE + 0x94) @@ -525,6 +526,7 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) } hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, prog_phy_link_rate); + hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00); hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);