From patchwork Wed Apr 27 12:26:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Saxena X-Patchwork-Id: 567014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0F94C433F5 for ; Wed, 27 Apr 2022 12:27:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233930AbiD0MaU (ORCPT ); Wed, 27 Apr 2022 08:30:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233906AbiD0MaT (ORCPT ); Wed, 27 Apr 2022 08:30:19 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 607724AE31 for ; Wed, 27 Apr 2022 05:27:04 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id q8so1409613plx.3 for ; Wed, 27 Apr 2022 05:27:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:mime-version; bh=sL93LAI/DwRt3nniBBG3i0px1z7k7J2na43aFZg+o0M=; b=DV7r9bLRDlt96San7R1GvGrZVEG4cn+ph0eBy983aaIV5evOoUj/bltvJKoIopfQ43 IfdXN0Zjy8LXPtrCCWkElMHOQtsC6vcZw0JSdqpAyRas7S7m2acXqb/N7CNM9spqMa8E IIpYXpuGGsLyaAdqOZduFGo5SZV9QHYBnG9v4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version; bh=sL93LAI/DwRt3nniBBG3i0px1z7k7J2na43aFZg+o0M=; b=MDn8CO3diwHXoipC0KgokbrewhaYkE9RXgdLl3RtYk2nEfnHq+a4jGXxDvb4P6UNqz 4+cfSPhejwz0KDH/VcawJoG5MDGC0ALGNTb0DlMXp2VRlLZIBKswC8nzoB/NoifvT301 Ha6R3yiemYPINToEWx+4QGJCpMRjlcIY4XqSrvWDuZTvRQWvh/HAfdURDD74gh1XW/ll catJGYEILAKJKYhDm7GjMxZSQUymLVOMozYB5UVWIlSpI9WsQ+GkVtrdaIvfFVpLNXpW bbTn3k4eSA5+RIpmSihYzWxs7gfO+1wgJq2z/9PfBkA+r5uEW7jGreZtK0Q+xjHNthto DX4Q== X-Gm-Message-State: AOAM5308gDoInqJzlCjwK+Tayvd8BHvhAU/Zvs1cQUoLAqOjVumEub77 n0QfLNJzldN+JpzVgUiRoI9KisMv7WEpkLaSB9CKp9ztlU9rYuvi3ciiviKPxZ7D5V1wbSMzaB6 gEgRL7IE1K3cdNAHj2OugE5C1I2Go3WsxwhecudajOFkjsXopDgpuT+70jaGx30XEy+sC/Lquj6 steBZi5uI= X-Google-Smtp-Source: ABdhPJzXNC0SJiVpLbSubQyYO95SeF8EopcYNTSfvG4/6Y5mbzuKZ7wPl+s/5nSTjkZj3FbslOBFpQ== X-Received: by 2002:a17:903:213:b0:156:7efe:4783 with SMTP id r19-20020a170903021300b001567efe4783mr28406966plh.126.1651062423381; Wed, 27 Apr 2022 05:27:03 -0700 (PDT) Received: from dhcp-10-123-20-15.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id h195-20020a6283cc000000b0050d2c0729b0sm14088296pfe.18.2022.04.27.05.27.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Apr 2022 05:27:02 -0700 (PDT) From: Sumit Saxena To: linux-scsi@vger.kernel.org Cc: martin.petersen@oracle.com, Sumit Saxena , Stephen Rothwell Subject: [PATCH] uapi: Fix build errors in uapi header scsi_bsg_mpi3mr.h Date: Wed, 27 Apr 2022 08:26:22 -0400 Message-Id: <20220427122622.543126-1-sumit.saxena@broadcom.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Fixed build errors reported during x86_64 allmodconfig and few spaces to tabs conversions. Fixes: a212ebe7d4b1 ("scsi: mpi3mr: Add support for driver commands") Fixes: 455aac4f7a13 ("scsi: mpi3mr: Move data structures/definitions from MPI headers to uapi header") Reported-by: Stephen Rothwell Signed-off-by: Sumit Saxena --- include/uapi/scsi/scsi_bsg_mpi3mr.h | 292 ++++++++++++++-------------- 1 file changed, 147 insertions(+), 145 deletions(-) diff --git a/include/uapi/scsi/scsi_bsg_mpi3mr.h b/include/uapi/scsi/scsi_bsg_mpi3mr.h index 46c33efcff19..fdc3517f9e19 100644 --- a/include/uapi/scsi/scsi_bsg_mpi3mr.h +++ b/include/uapi/scsi/scsi_bsg_mpi3mr.h @@ -10,6 +10,8 @@ #ifndef SCSI_BSG_MPI3MR_H_INCLUDED #define SCSI_BSG_MPI3MR_H_INCLUDED +#include + /* Definitions for BSG commands */ #define MPI3MR_IOCTL_VERSION 0x06 @@ -93,14 +95,14 @@ enum command { * @driver_capabilities: Driver capabilities */ struct mpi3_driver_info_layout { - __le32 information_length; - u8 driver_signature[12]; - u8 os_name[16]; - u8 os_version[12]; - u8 driver_name[20]; - u8 driver_version[32]; - u8 driver_release_date[20]; - __le32 driver_capabilities; + __le32 information_length; + __u8 driver_signature[12]; + __u8 os_name[16]; + __u8 os_version[12]; + __u8 driver_name[20]; + __u8 driver_version[32]; + __u8 driver_release_date[20]; + __le32 driver_capabilities; }; /** @@ -125,22 +127,22 @@ struct mpi3_driver_info_layout { * @driver_info: Driver Information (Version/Name) */ struct mpi3mr_bsg_in_adpinfo { - uint32_t adp_type; - uint32_t rsvd1; - uint32_t pci_dev_id; - uint32_t pci_dev_hw_rev; - uint32_t pci_subsys_dev_id; - uint32_t pci_subsys_ven_id; - uint32_t pci_dev:5; - uint32_t pci_func:3; - uint32_t pci_bus:8; - uint16_t rsvd2; - uint32_t pci_seg_id; - uint32_t app_intfc_ver; - uint8_t adp_state; - uint8_t rsvd3; - uint16_t rsvd4; - uint32_t rsvd5[2]; + __u32 adp_type; + __u32 rsvd1; + __u32 pci_dev_id; + __u32 pci_dev_hw_rev; + __u32 pci_subsys_dev_id; + __u32 pci_subsys_ven_id; + __u32 pci_dev:5; + __u32 pci_func:3; + __u32 pci_bus:8; + __u16 rsvd2; + __u32 pci_seg_id; + __u32 app_intfc_ver; + __u8 adp_state; + __u8 rsvd3; + __u16 rsvd4; + __u32 rsvd5[2]; struct mpi3_driver_info_layout driver_info; }; @@ -153,9 +155,9 @@ struct mpi3mr_bsg_in_adpinfo { * @rsvd2: Reserved */ struct mpi3mr_bsg_adp_reset { - uint8_t reset_type; - uint8_t rsvd1; - uint16_t rsvd2; + __u8 reset_type; + __u8 rsvd1; + __u16 rsvd2; }; /** @@ -166,8 +168,8 @@ struct mpi3mr_bsg_adp_reset { * @rsvd: Reserved */ struct mpi3mr_change_count { - uint16_t change_count; - uint16_t rsvd; + __u16 change_count; + __u16 rsvd; }; /** @@ -182,12 +184,12 @@ struct mpi3mr_change_count { * @rsvd2: Reserved */ struct mpi3mr_device_map_info { - uint16_t handle; - uint16_t perst_id; - uint32_t target_id; - uint8_t bus_id; - uint8_t rsvd1; - uint16_t rsvd2; + __u16 handle; + __u16 perst_id; + __u32 target_id; + __u8 bus_id; + __u8 rsvd1; + __u16 rsvd2; }; /** @@ -200,9 +202,9 @@ struct mpi3mr_device_map_info { * @dmi: Variable length array of mapping information of targets */ struct mpi3mr_all_tgt_info { - uint16_t num_devices; - uint16_t rsvd1; - uint32_t rsvd2; + __u16 num_devices; + __u16 rsvd1; + __u32 rsvd2; struct mpi3mr_device_map_info dmi[1]; }; @@ -215,8 +217,8 @@ struct mpi3mr_all_tgt_info { * @rsvd: Reserved */ struct mpi3mr_logdata_enable { - uint16_t max_entries; - uint16_t rsvd; + __u16 max_entries; + __u16 rsvd; }; /** @@ -228,9 +230,9 @@ struct mpi3mr_logdata_enable { * @rsvd: Reserved */ struct mpi3mr_bsg_out_pel_enable { - uint16_t pel_locale; - uint8_t pel_class; - uint8_t rsvd; + __u16 pel_locale; + __u8 pel_class; + __u8 rsvd; }; /** @@ -243,10 +245,10 @@ struct mpi3mr_bsg_out_pel_enable { * @data: Variable length Log entry data */ struct mpi3mr_logdata_entry { - uint8_t valid_entry; - uint8_t rsvd1; - uint16_t rsvd2; - uint8_t data[1]; /* Variable length Array */ + __u8 valid_entry; + __u8 rsvd1; + __u16 rsvd2; + __u8 data[1]; /* Variable length Array */ }; /** @@ -274,15 +276,15 @@ struct mpi3mr_bsg_in_log_data { * @rsvd4: Reserved */ struct mpi3mr_hdb_entry { - uint8_t buf_type; - uint8_t status; - uint8_t trigger_type; - uint8_t rsvd1; - uint16_t size; - uint16_t rsvd2; - uint64_t trigger_data; - uint32_t rsvd3; - uint32_t rsvd4; + __u8 buf_type; + __u8 status; + __u8 trigger_type; + __u8 rsvd1; + __u16 size; + __u16 rsvd2; + __u64 trigger_data; + __u32 rsvd3; + __u32 rsvd4; }; @@ -300,10 +302,10 @@ struct mpi3mr_hdb_entry { * @entry: Variable length Diag buffer status entry array */ struct mpi3mr_bsg_in_hdb_status { - uint8_t num_hdb_types; - uint8_t rsvd1; - uint16_t rsvd2; - uint32_t rsvd3; + __u8 num_hdb_types; + __u8 rsvd1; + __u16 rsvd2; + __u32 rsvd3; struct mpi3mr_hdb_entry entry[1]; }; @@ -316,9 +318,9 @@ struct mpi3mr_bsg_in_hdb_status { * @rsvd2: Reserved */ struct mpi3mr_bsg_out_repost_hdb { - uint8_t buf_type; - uint8_t rsvd1; - uint16_t rsvd2; + __u8 buf_type; + __u8 rsvd1; + __u16 rsvd2; }; /** @@ -332,11 +334,11 @@ struct mpi3mr_bsg_out_repost_hdb { * @length: Length of the buffer to copy */ struct mpi3mr_bsg_out_upload_hdb { - uint8_t buf_type; - uint8_t rsvd1; - uint16_t rsvd2; - uint32_t start_offset; - uint32_t length; + __u8 buf_type; + __u8 rsvd1; + __u16 rsvd2; + __u32 start_offset; + __u32 length; }; /** @@ -348,9 +350,9 @@ struct mpi3mr_bsg_out_upload_hdb { * @rsvd2: Reserved */ struct mpi3mr_bsg_out_refresh_hdb_triggers { - uint8_t page_type; - uint8_t rsvd1; - uint16_t rsvd2; + __u8 page_type; + __u8 rsvd1; + __u16 rsvd2; }; /** * struct mpi3mr_bsg_drv_cmd - Generic bsg data @@ -362,10 +364,10 @@ struct mpi3mr_bsg_out_refresh_hdb_triggers { * @rsvd2: Reserved */ struct mpi3mr_bsg_drv_cmd { - uint8_t mrioc_id; - uint8_t opcode; - uint16_t rsvd1; - uint32_t rsvd2[4]; + __u8 mrioc_id; + __u8 opcode; + __u16 rsvd1; + __u32 rsvd2[4]; }; /** * struct mpi3mr_bsg_in_reply_buf - MPI reply buffer returned @@ -377,10 +379,10 @@ struct mpi3mr_bsg_drv_cmd { * @reply_buf: Variable Length buffer based on mpirep type */ struct mpi3mr_bsg_in_reply_buf { - uint8_t mpi_reply_type; - uint8_t rsvd1; - uint16_t rsvd2; - uint8_t reply_buf[1]; + __u8 mpi_reply_type; + __u8 rsvd1; + __u16 rsvd2; + __u8 reply_buf[1]; }; /** @@ -393,10 +395,10 @@ struct mpi3mr_bsg_in_reply_buf { * @buf_len: Buffer length */ struct mpi3mr_buf_entry { - uint8_t buf_type; - uint8_t rsvd1; - uint16_t rsvd2; - uint32_t buf_len; + __u8 buf_type; + __u8 rsvd1; + __u16 rsvd2; + __u32 buf_len; }; /** * struct mpi3mr_bsg_buf_entry_list - list of user buffer @@ -409,10 +411,10 @@ struct mpi3mr_buf_entry { * @buf_entry: Variable length array of buffer descriptors */ struct mpi3mr_buf_entry_list { - uint8_t num_of_entries; - uint8_t rsvd1; - uint16_t rsvd2; - uint32_t rsvd3; + __u8 num_of_entries; + __u8 rsvd1; + __u16 rsvd2; + __u32 rsvd3; struct mpi3mr_buf_entry buf_entry[1]; }; /** @@ -425,10 +427,10 @@ struct mpi3mr_buf_entry_list { * @buf_entry_list: Buffer descriptor list */ struct mpi3mr_bsg_mptcmd { - uint8_t mrioc_id; - uint8_t rsvd1; - uint16_t timeout; - uint32_t rsvd2; + __u8 mrioc_id; + __u8 rsvd1; + __u16 timeout; + __u32 rsvd2; struct mpi3mr_buf_entry_list buf_entry_list; }; @@ -443,10 +445,10 @@ struct mpi3mr_bsg_mptcmd { * @mptcmd: mpt request structure */ struct mpi3mr_bsg_packet { - uint8_t cmd_type; - uint8_t rsvd1; - uint16_t rsvd2; - uint32_t rsvd3; + __u8 cmd_type; + __u8 rsvd1; + __u16 rsvd2; + __u32 rsvd3; union { struct mpi3mr_bsg_drv_cmd drvrcmd; struct mpi3mr_bsg_mptcmd mptcmd; @@ -460,32 +462,32 @@ struct mpi3mr_bsg_packet { #endif struct mpi3_nvme_encapsulated_request { - __le16 host_tag; - u8 ioc_use_only02; - u8 function; - __le16 ioc_use_only04; - u8 ioc_use_only06; - u8 msg_flags; - __le16 change_count; - __le16 dev_handle; - __le16 encapsulated_command_length; - __le16 flags; - __le32 data_length; - __le32 reserved14[3]; - __le32 command[MPI3_NVME_ENCAP_CMD_MAX]; + __le16 host_tag; + __u8 ioc_use_only02; + __u8 function; + __le16 ioc_use_only04; + __u8 ioc_use_only06; + __u8 msg_flags; + __le16 change_count; + __le16 dev_handle; + __le16 encapsulated_command_length; + __le16 flags; + __le32 data_length; + __le32 reserved14[3]; + __le32 command[MPI3_NVME_ENCAP_CMD_MAX]; }; struct mpi3_nvme_encapsulated_error_reply { - __le16 host_tag; - u8 ioc_use_only02; - u8 function; - __le16 ioc_use_only04; - u8 ioc_use_only06; - u8 msg_flags; - __le16 ioc_use_only08; - __le16 ioc_status; - __le32 ioc_log_info; - __le32 nvme_completion_entry[4]; + __le16 host_tag; + __u8 ioc_use_only02; + __u8 function; + __le16 ioc_use_only04; + __u8 ioc_use_only06; + __u8 msg_flags; + __le16 ioc_use_only08; + __le16 ioc_status; + __le32 ioc_log_info; + __le32 nvme_completion_entry[4]; }; #define MPI3MR_NVME_PRP_SIZE 8 /* PRP size */ @@ -498,21 +500,21 @@ struct mpi3_nvme_encapsulated_error_reply { /* MPI3: task management related definitions */ struct mpi3_scsi_task_mgmt_request { - __le16 host_tag; - u8 ioc_use_only02; - u8 function; - __le16 ioc_use_only04; - u8 ioc_use_only06; - u8 msg_flags; - __le16 change_count; - __le16 dev_handle; - __le16 task_host_tag; - u8 task_type; - u8 reserved0f; - __le16 task_request_queue_id; - __le16 reserved12; - __le32 reserved14; - u8 lun[8]; + __le16 host_tag; + __u8 ioc_use_only02; + __u8 function; + __le16 ioc_use_only04; + __u8 ioc_use_only06; + __u8 msg_flags; + __le16 change_count; + __le16 dev_handle; + __le16 task_host_tag; + __u8 task_type; + __u8 reserved0f; + __le16 task_request_queue_id; + __le16 reserved12; + __le32 reserved14; + __u8 lun[8]; }; #define MPI3_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x08) @@ -527,18 +529,18 @@ struct mpi3_scsi_task_mgmt_request { #define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_ASYNC_EVENT (0x0a) #define MPI3_SCSITASKMGMT_TASKTYPE_I_T_NEXUS_RESET (0x0b) struct mpi3_scsi_task_mgmt_reply { - __le16 host_tag; - u8 ioc_use_only02; - u8 function; - __le16 ioc_use_only04; - u8 ioc_use_only06; - u8 msg_flags; - __le16 ioc_use_only08; - __le16 ioc_status; - __le32 ioc_log_info; - __le32 termination_count; - __le32 response_data; - __le32 reserved18; + __le16 host_tag; + __u8 ioc_use_only02; + __u8 function; + __le16 ioc_use_only04; + __u8 ioc_use_only06; + __u8 msg_flags; + __le16 ioc_use_only08; + __le16 ioc_status; + __le32 ioc_log_info; + __le32 termination_count; + __le32 response_data; + __le32 reserved18; }; #define MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE (0x00)