From patchwork Mon Aug 1 12:41:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sreekanth Reddy X-Patchwork-Id: 594818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52712C19F2A for ; Mon, 1 Aug 2022 12:44:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232120AbiHAMof (ORCPT ); Mon, 1 Aug 2022 08:44:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234417AbiHAMoP (ORCPT ); Mon, 1 Aug 2022 08:44:15 -0400 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33B9B402E1 for ; Mon, 1 Aug 2022 05:29:37 -0700 (PDT) Received: by mail-pg1-x534.google.com with SMTP id r186so9544309pgr.2 for ; Mon, 01 Aug 2022 05:29:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc; bh=LlXXGTp/SgccJILfZkbL6Ll4YFaRYBGiN5W0leAPczo=; b=dKxUjGJwbHfoyfASGnqYhwWF5ajoMIf6fERJRTpc0SRumEI5switgnQjCYODzWlq0M uE/HluhU07yzGjVGg4gxaVl8Wx8cirZcO07QF8XwAcgTd9rHxE3k/11wTB7c6pM28FSw +fFbw73RUg56Ys7/3aoRO9pfXT7Wu42VoYuCQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc; bh=LlXXGTp/SgccJILfZkbL6Ll4YFaRYBGiN5W0leAPczo=; b=5hXlKLWt1zS7TQphsrBlCrdg8CRpGxdmEu7nVc+uqIl6QI7vPviz6aWgQWx2zLJGgI 8TJTnXOJj+KKWtL8SF22yk3IkmLas4UkpUAHznSKWnenIvG10IDPzcudvkeFF0Ju6Wxi oRAV5zBgcG9zSuUa/UxqMV6Dt64ttOPoxCtsAqoDV7mE+GpDfUwOvgJcsPsWbuNBQp7X nUGILblehlqLamhMVF8xVvVFEQjH5j1fzhPjn97g1q8ZSatPZxx7X6TeMVq4TcNk1fVy BLi28H4s3odw2t3fhjgLUJtNVP1XqYL1pFpaZoKUo2zHXiwfBB8oeMYpENgeySj3aBOv EP+Q== X-Gm-Message-State: AJIora9WzBvoE51YROwEhGMAQehdLrrIvm09G+2Ih84We6+7eKIglDoR 7iqFqP0TOFqUMxLxJQI8TUbiP7YtQyJ5JygPUix3h16DOp0D0omsTUW0PDSOYf02XAIsNzrbrwj WQTDumfUsngtWW4PnApw5p3dNdOcwNx63HLQyDvn/y4gDrft+8EOiy8HXSrWeuHszqH6aWhJm/d RIVSHCCqrp X-Google-Smtp-Source: AGRyM1s8H5jxutoIT2MUxAXNQEfIifLjicBmEE8shf3SLnMtyzAz10Bs3Yi3ouc2/ee2vsf5HyQcTw== X-Received: by 2002:a05:6a00:1901:b0:4fa:fa9e:42e6 with SMTP id y1-20020a056a00190100b004fafa9e42e6mr16044686pfi.1.1659356976228; Mon, 01 Aug 2022 05:29:36 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id u3-20020a17090add4300b001f260b1954bsm8931912pjv.13.2022.08.01.05.29.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Aug 2022 05:29:35 -0700 (PDT) From: Sreekanth Reddy To: linux-scsi@vger.kernel.org Cc: martin.petersen@oracle.com, Sreekanth Reddy Subject: [PATCH 1/4] mpt3sas: Don't change dma mask while reallocating pools Date: Mon, 1 Aug 2022 18:11:41 +0530 Message-Id: <20220801124144.11458-2-sreekanth.reddy@broadcom.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220801124144.11458-1-sreekanth.reddy@broadcom.com> References: <20220801124144.11458-1-sreekanth.reddy@broadcom.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org When a pool crosses the 4gb boundary region then before reallocation pools just change the coherent dma mask to 32bit and keep the normal dma mask to 63/64 bit. Signed-off-by: Sreekanth Reddy --- drivers/scsi/mpt3sas/mpt3sas_base.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 565339a..e257e0d 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -2990,19 +2990,26 @@ static int _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) { struct sysinfo s; + u64 coherent_dma_mask, dma_mask; - if (ioc->is_mcpu_endpoint || - sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma || - dma_get_required_mask(&pdev->dev) <= 32) + if (ioc->is_mcpu_endpoint || sizeof(dma_addr_t) == 4 || + dma_get_required_mask(&pdev->dev) <= 32) { ioc->dma_mask = 32; + coherent_dma_mask = dma_mask = DMA_BIT_MASK(32); /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */ - else if (ioc->hba_mpi_version_belonged > MPI2_VERSION) + } else if (ioc->hba_mpi_version_belonged > MPI2_VERSION) { ioc->dma_mask = 63; - else + coherent_dma_mask = dma_mask = DMA_BIT_MASK(63); + } else { ioc->dma_mask = 64; + coherent_dma_mask = dma_mask = DMA_BIT_MASK(64); + } + + if (ioc->use_32bit_dma) + coherent_dma_mask = DMA_BIT_MASK(32); - if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)) || - dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask))) + if (dma_set_mask(&pdev->dev, dma_mask) || + dma_set_coherent_mask(&pdev->dev, coherent_dma_mask)) return -ENODEV; if (ioc->dma_mask > 32) {