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Tue, 23 Apr 2024 13:50:21 -0700 (PDT) Received: from gpeter-l.lan ([2a0d:3344:2e8:8510:4269:2542:5a09:9ca1]) by smtp.gmail.com with ESMTPSA id bg5-20020a05600c3c8500b00419f419236fsm13065443wmb.41.2024.04.23.13.50.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Apr 2024 13:50:21 -0700 (PDT) From: Peter Griffin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, jejb@linux.ibm.com, martin.petersen@oracle.com, James.Bottomley@HansenPartnership.com, ebiggers@kernel.org Cc: linux-scsi@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, Peter Griffin Subject: [PATCH v2 05/14] arm64: dts: exynos: gs101: Add the hsi2 sysreg node Date: Tue, 23 Apr 2024 21:49:57 +0100 Message-ID: <20240423205006.1785138-6-peter.griffin@linaro.org> X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog In-Reply-To: <20240423205006.1785138-1-peter.griffin@linaro.org> References: <20240423205006.1785138-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This has some configuration bits such as sharability that are required by UFS. Signed-off-by: Peter Griffin Reviewed-by: André Draszik --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 38ac4fb1397e..09044deede63 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 { clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card"; }; + sysreg_hsi2: syscon@14420000 { + compatible = "google,gs101-hsi2-sysreg", "syscon"; + reg = <0x14420000 0x10000>; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>;