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AJvYcCUdSe0m5GlT7SpRYC/j3qCWM1US2ZGkg6iKKcrWAbwiF8KNypCjva4ZqtQ0CGWl6f9UBpACg/SdF7U+@vger.kernel.org X-Gm-Message-State: AOJu0Yywdul8Rg4VD49jXyO6k5jMxfym0sATfhwsXCob2/rNAQ2A7hdr 1NzhiLdQ0pVPigtqL4QehaBvQ2SFLnnpCN7MF+ePOCqEC5CAJuFkrTlkhghZhPU= X-Google-Smtp-Source: AGHT+IFn4umTFqPxopB2GAJY2aOrR7RfiFspVJ8SdEfcnoO13PLJi0jzfHRWD2Ee5O6gR0xA2R/rxA== X-Received: by 2002:a05:600c:3b2a:b0:42c:af2a:dcf4 with SMTP id 5b1f17b1804b1-4318c754f00mr39202585e9.27.1729862104292; Fri, 25 Oct 2024 06:15:04 -0700 (PDT) Received: from gpeter-l.lan ([145.224.67.228]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4318b58b6bdsm47616685e9.45.2024.10.25.06.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 06:15:03 -0700 (PDT) From: Peter Griffin To: alim.akhtar@samsung.com, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, avri.altman@wdc.com, bvanassche@acm.org, krzk@kernel.org Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, kernel-team@android.com, willmcvicker@google.com, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@kernel.org, Peter Griffin Subject: [PATCH v2 11/11] scsi: ufs: exynos: gs101: enable clock gating with hibern8 Date: Fri, 25 Oct 2024 14:14:42 +0100 Message-ID: <20241025131442.112862-12-peter.griffin@linaro.org> X-Mailer: git-send-email 2.47.0.163.g1226f6d8fa-goog In-Reply-To: <20241025131442.112862-1-peter.griffin@linaro.org> References: <20241025131442.112862-1-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable clock gating and hibern8 capabilities for gs101. This leads to a significantly cooler phone when running the upstream kernel. The exynos_ufs_post_hibern8() hook is also updated to remove the UIC_CMD_DME_HIBER_EXIT code path as this causes a hang on gs101. The code path is removed rather than re-factored as no other SoC in ufs-exynos driver sets UFSHCD_CAP_HIBERN8_WITH_CLK_GATING capability. Additionally until the previous commit the hibern8 callbacks were broken anyway as they expected a bool. Signed-off-by: Peter Griffin Reviewed-by: Tudor Ambarus --- drivers/ufs/host/ufs-exynos.c | 24 ++++-------------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 3bbb71f7bae7..7c8195f27bb6 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -229,6 +229,9 @@ static int gs101_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs) /* Enable WriteBooster */ hba->caps |= UFSHCD_CAP_WB_EN; + /* Enable clock gating and hibern8 */ + hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; + /* set ACG to be controlled by UFS_ACG_DISABLE */ reg = hci_readl(ufs, HCI_IOP_ACG_DISABLE); hci_writel(ufs, reg & (~HCI_IOP_ACG_DISABLE_EN), HCI_IOP_ACG_DISABLE); @@ -1566,26 +1569,7 @@ static void exynos_ufs_post_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd) { struct exynos_ufs *ufs = ufshcd_get_variant(hba); - if (cmd == UIC_CMD_DME_HIBER_EXIT) { - u32 cur_mode = 0; - u32 pwrmode; - - if (ufshcd_is_hs_mode(&ufs->dev_req_params)) - pwrmode = FAST_MODE; - else - pwrmode = SLOW_MODE; - - ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode); - if (cur_mode != (pwrmode << 4 | pwrmode)) { - dev_warn(hba->dev, "%s: power mode change\n", __func__); - hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf; - hba->pwr_info.pwr_tx = cur_mode & 0xf; - ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); - } - - if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)) - exynos_ufs_establish_connt(ufs); - } else if (cmd == UIC_CMD_DME_HIBER_ENTER) { + if (cmd == UIC_CMD_DME_HIBER_ENTER) { ufs->entry_hibern8_t = ktime_get(); exynos_ufs_gate_clks(ufs); if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)