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Bottomley" , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 3/3] scsi: ufs: qcom: Call ufs_qcom_cfg_timers() in clock scaling path Date: Fri, 2 May 2025 12:24:32 +0800 Message-Id: <20250502042432.88434-4-quic_ziqichen@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250502042432.88434-1-quic_ziqichen@quicinc.com> References: <20250502042432.88434-1-quic_ziqichen@quicinc.com> Precedence: bulk X-Mailing-List: linux-scsi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTAyMDAzMSBTYWx0ZWRfX+kqfcAqD8AlV txHr9Dy3Hoqa/4L8dCukqcelWAsJ9gbl/QjgGlBhfgDeshVP7IanNDmgXEuQHkOvfynUOyceR5j e48cX1RlSLKrP1MNTzw4JaxsxZEzwvFQi3+uQKNy12bibi4nkT/ON0wQ2prZxxW+VAgiJ8EQzv4 4RtyvHaQ2dB8KxK73NWEIJXrC14ombX5FjfbOjRjgM0ATTcPpA2HM4Jf8ZpS7d1Ezi72C4l3zSo mfAhT9XGsx8Xex9bkQD0D3pV4DlHG/u7Ei1D374z0Ft6/p50owAMXEiS9z1HBloVsMKMRDHBzhm jBvVx2XFESXEGlsh94Kb7Ba3MZWmNmRY3ScXExRGnrxRXIOc7dK/gmIVGFUus2WFjylc0Qemhb1 YhOoul2ubzn7NHiYU7DHq4LYHct0sgm+XKWQP/tfRPMOEPD+zmwTWUfqSfOV4k1QsGHk55cj X-Proofpoint-GUID: sJ9BF59YfxsZiMTieOfMAJeBwQBXcSgK X-Authority-Analysis: v=2.4 cv=W404VQWk c=1 sm=1 tr=0 ts=68144948 cx=c_pps a=nuhDOHQX5FNHPW3J6Bj6AA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=x4qbwuVvB1nHrQTLSukA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: sJ9BF59YfxsZiMTieOfMAJeBwQBXcSgK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-01_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 spamscore=0 clxscore=1015 phishscore=0 impostorscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505020031 From: Can Guo ufs_qcom_cfg_timers() is clock freq dependent like ufs_qcom_set_core_clk_ ctrl(), hence move ufs_qcom_cfg_timers() call to clock scaling path. In addition, do not assume the devfreq OPP freq is always the 'core_clock' freq although 'core_clock' is the first clock phandle in device tree, use ufs_qcom_opp_freq_to_clk_freq() to find the core clk freq. Signed-off-by: Can Guo Co-developed-by: Ziqi Chen Signed-off-by: Ziqi Chen --- drivers/ufs/host/ufs-qcom.c | 49 ++++++++++++++++++++++--------------- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 00ca0b577c96..895972bf44c0 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -576,13 +576,14 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, * * @hba: host controller instance * @is_pre_scale_up: flag to check if pre scale up condition. + * @freq: target opp freq * Return: zero for success and non-zero in case of a failure. */ -static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up) +static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up, unsigned long freq) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); struct ufs_clk_info *clki; - unsigned long core_clk_rate = 0; + unsigned long clk_freq = 0; u32 core_clk_cycles_per_us; /* @@ -594,22 +595,34 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, bool is_pre_scale_up) if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba)) return 0; + if (hba->use_pm_opp) { + clk_freq = ufs_qcom_opp_freq_to_clk_freq(hba, freq, "core_clk"); + if (clk_freq) + goto cfg_timers; + } + list_for_each_entry(clki, &hba->clk_list_head, list) { if (!strcmp(clki->name, "core_clk")) { + if (freq == ULONG_MAX) { + clk_freq = clki->max_freq; + break; + } + if (is_pre_scale_up) - core_clk_rate = clki->max_freq; + clk_freq = clki->max_freq; else - core_clk_rate = clk_get_rate(clki->clk); + clk_freq = clk_get_rate(clki->clk); break; } } +cfg_timers: /* If frequency is smaller than 1MHz, set to 1MHz */ - if (core_clk_rate < DEFAULT_CLK_RATE_HZ) - core_clk_rate = DEFAULT_CLK_RATE_HZ; + if (clk_freq < DEFAULT_CLK_RATE_HZ) + clk_freq = DEFAULT_CLK_RATE_HZ; - core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC; + core_clk_cycles_per_us = clk_freq / USEC_PER_SEC; if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); /* @@ -629,7 +642,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, switch (status) { case PRE_CHANGE: - if (ufs_qcom_cfg_timers(hba, false)) { + if (ufs_qcom_cfg_timers(hba, false, ULONG_MAX)) { dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); return -EINVAL; @@ -885,17 +898,6 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, } break; case POST_CHANGE: - if (ufs_qcom_cfg_timers(hba, false)) { - dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", - __func__); - /* - * we return error code at the end of the routine, - * but continue to configure UFS_PHY_TX_LANE_ENABLE - * and bus voting as usual - */ - ret = -EINVAL; - } - /* cache the power mode parameters to use internally */ memcpy(&host->dev_req_params, dev_req_params, sizeof(*dev_req_params)); @@ -1430,7 +1432,7 @@ static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba, unsigned long f { int ret; - ret = ufs_qcom_cfg_timers(hba, true); + ret = ufs_qcom_cfg_timers(hba, true, freq); if (ret) { dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__); return ret; @@ -1467,6 +1469,13 @@ static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba, unsigned long freq) { + int ret; + + ret = ufs_qcom_cfg_timers(hba, false, freq); + if (ret) { + dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); + return ret; + } /* set unipro core clock attributes and clear clock divider */ return ufs_qcom_set_core_clk_ctrl(hba, false, freq); }