| Message ID | 20230110003029.806022-1-matthew.gerlach@linux.intel.com |
|---|---|
| Headers | show |
| Series | Enhance definition of DFH and use enhancements for UART driver | expand |
On Mon, Jan 09, 2023 at 04:30:29PM -0800, matthew.gerlach@linux.intel.com wrote: > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > Add a Device Feature List (DFL) bus driver for the Altera > 16550 implementation of UART. ... > +static int dfh_get_u64_param_val(struct dfl_device *dfl_dev, int param_id, u64 *pval) > +{ > + size_t psize; > + u64 *p; > + > + p = dfh_find_param(dfl_dev, param_id, &psize); > + if (IS_ERR(p)) > + return PTR_ERR(p); > + if (psize != sizeof(u64)) > + return -EINVAL; If this code stays in the newer versions, make it more robust against changes, i.e. by using sizeof(*pval). > + *pval = *p; > + > + return 0; > +} ... > +config SERIAL_8250_DFL > + tristate "DFL bus driver for Altera 16550 UART" 5 > + depends on SERIAL_8250 && FPGA_DFL > + help > + This option enables support for a Device Feature List (DFL) bus > + driver for the Altera 16650 UART. One or more Altera 16650 UARTs 6 Which one is correct? > + can be instantiated in a FPGA and then be discovered during > + enumeration of the DFL bus. > + > + To compile this driver as a module, chose M here: the > + module will be called 8250_dfl.
From: Matthew Gerlach <matthew.gerlach@linux.intel.com> This patchset enhances the definition of the Device Feature Header (DFH) used by the Device Feature List (DFL) bus and then uses the new enhancements in a UART driver. The enhancements to the DFH includes the introduction of parameter blocks. Like PCI capabilities, the DFH parameter blocks further describe the hardware to software. In the case of the UART, the parameter blocks provide information for the interrupt, clock frequency, and register layout. Duplication of code parsing of the parameter blocks in multiple DFL drivers is a concern. Using swnodes was considered to help minimize parsing code duplication, but their use did not help the problem. Furthermore the highly changeable nature of FPGAs employing the DFL bus makes the use of swnodes inappropriate. Patch 1 updates the DFL documentation to describe the added functionality to DFH. Patch 2 adds the definitions for DFHv1. Patch 3 adds basic support for DFHv1. It adds functionality to parse parameter blocks and adds the functionality to parse the explicit location of a feature's register set. Patch 4 adds a DFL UART driver that makes use of the new features of DFHv1. Basheer Ahmed Muddebihal (1): fpga: dfl: Add DFHv1 Register Definitions Matthew Gerlach (3): Documentation: fpga: dfl: Add documentation for DFHv1 fpga: dfl: add basic support for DFHv1 tty: serial: 8250: add DFL bus driver for Altera 16550. Documentation/fpga/dfl.rst | 117 ++++++++++++++ drivers/fpga/dfl.c | 245 +++++++++++++++++++++++------ drivers/fpga/dfl.h | 43 +++++ drivers/tty/serial/8250/8250_dfl.c | 167 ++++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 12 ++ drivers/tty/serial/8250/Makefile | 1 + include/linux/dfl.h | 8 + 7 files changed, 542 insertions(+), 51 deletions(-) create mode 100644 drivers/tty/serial/8250/8250_dfl.c