[0/2] add NXP LINFlexD UART clock support for S32G2/S32G3 SoC

Message ID	20240924141247.132455-1-ciprianmarian.costea@oss.nxp.com
Headers	show Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2068.outbound.protection.outlook.com [40.107.22.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1549E1B85D5; Tue, 24 Sep 2024 14:12:58 +0000 (UTC) From: Ciprian Costea <ciprianmarian.costea@oss.nxp.com> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Chester Lin <chester62515@gmail.com> Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, NXP S32 Linux Team <s32@nxp.com>, Christophe Lizzi <clizzi@redhat.com>, Alberto Ruiz <aruizrui@redhat.com>, Enric Balletbo <eballetb@redhat.com>, Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Subject: [PATCH 0/2] add NXP LINFlexD UART clock support for S32G2/S32G3 SoC Date: Tue, 24 Sep 2024 17:12:45 +0300 Message-ID: <20240924141247.132455-1-ciprianmarian.costea@oss.nxp.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1
Series	add NXP LINFlexD UART clock support for S32G2/S32G3 SoC \| expand [0/2] add NXP LINFlexD UART clock support for S32G2/S32G3 SoC [1/2] dt-bindings: linflexuart: add clock definitions [2/2] serial: fsl_linflexuart: add clock support

Message ID

20240924141247.132455-1-ciprianmarian.costea@oss.nxp.com

Headers

From: Ciprian Costea <ciprianmarian.costea@oss.nxp.com>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jiri Slaby <jirislaby@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Chester Lin <chester62515@gmail.com>
Cc: linux-kernel@vger.kernel.org,
	linux-serial@vger.kernel.org,
	devicetree@vger.kernel.org,
	NXP S32 Linux Team <s32@nxp.com>,
	Christophe Lizzi <clizzi@redhat.com>,
	Alberto Ruiz <aruizrui@redhat.com>,
	Enric Balletbo <eballetb@redhat.com>,
	Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Subject: [PATCH 0/2] add NXP LINFlexD UART clock support for S32G2/S32G3 SoC
Date: Tue, 24 Sep 2024 17:12:45 +0300
Message-ID: <20240924141247.132455-1-ciprianmarian.costea@oss.nxp.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-MessageSentRepresentingType: 1
X-MS-PublicTrafficType: Email
X-MS-TrafficTypeDiagnostic: DU0PR04MB9251:EE_|DB9PR04MB9791:EE_
X-MS-Office365-Filtering-Correlation-Id: a985112a-1e20-40fb-12e2-08dcdca2f91f
X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True
X-MS-Exchange-SenderADCheck: 1
X-MS-Exchange-AntiSpam-Relay: 0
X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|366016|1800799024;
X-Microsoft-Antispam-Message-Info: =?utf-8?q?UY2jgjumP07m1ujosNSkb29aTOEQR0c?=
	=?utf-8?q?JWdGnpq0L/+kkLpjdHLL1qmXfno5kjbCDf6bdujw8xTfCZw9j493Vven8Y8FwwXKM?=
	=?utf-8?q?XYtUrMF5D39QfraPwTcF+vpvfPfEdsK5aV6+RJCppipB2Ac7EGkDS9cHaTjRCqzQP?=
	=?utf-8?q?R9ySc8ZA3vXHhQevp5Q1B4RMdQk6ZzriT3a85lj9uJIHSxFkW8THzXI/W6svGqvHf?=
	=?utf-8?q?aqnYHYiNCUqzUki6tgvRqrEveA20KKPCSQzKtqEJqjQERpcXas3lhX4sXOfDA+Cm5?=
	=?utf-8?q?UopVd4/1mMiYo96gHNQT5h79W6JC1enep745vyhGXqGGkuZRy+PVwMC7h4hU+jIXD?=
	=?utf-8?q?Ky5MBNBg92aOgMAM41ptbej/6aEJc6YQ7y6GIJ0DjRrVyEzHVK0gZQ+Y9VeHPaXS/?=
	=?utf-8?q?+ilTZTnclsf2e/OQYvMvPf7FxifWo925KGvl8HgBl3X8Y/ml/UfK1u8KqLbrpWA5h?=
	=?utf-8?q?G3qHOCm2hfFOW1veqIQFcfam+01CV1JyCQYOrfbAFTvwJv3du4MHWvAhOJN8AXCfC?=
	=?utf-8?q?UP1WZ0kHCsGCp6CjF5DwURdZ47Co+8rEeq2asCqNNyEHVAz9AIHEgvjQHB0FcsI3w?=
	=?utf-8?q?OP1O96nWhBhKcI9kYYc4EzI4J0gc/fNfUcSDdjyi81+70iohClo+wSLr023Ckny82?=
	=?utf-8?q?bt8VM3M/7M9MdzLCgLMl0MEWx6lEmpyaQTcowXH7Dc7fXE13dNdczcw2ufhcml29c?=
	=?utf-8?q?lNt8Uee5B0dFYQkm71BiubeyCBan9mdK5LFCK9UrKFtjmQJu2FdKgLKw/ZlV9Mj8w?=
	=?utf-8?q?qmUeL6xEmN7ZvIg2iwp2EF/ODICJmnP3gCqahldC8BjyhPVyb3k8b8pk999U7VNqv?=
	=?utf-8?q?k09WImWLRDrndEU5mYI3IsxUmkAoQg08xTT+CgR+rtzrcxo37xpvvIVhtLwOn2t3U?=
	=?utf-8?q?GlzbfC1RBidrV0AocJgNI2E9MnxM4cgcPvcO8a2YhUoAFMEBSEcN7/yAkM+MeWRnu?=
	=?utf-8?q?aPIOGQ0cmk1AMkMgI9qqWYKObgDrUVvPkje0S6Pe1sfOZAxKx8KtM/pkiZ5y9he7k?=
	=?utf-8?q?2Mh5iEIoGspXasvDp7ElUdwNIoi9hbXfuM9azwUXUoaHRj1keWdLXKdLwUjf5LrZM?=
	=?utf-8?q?Upsfn9a1kBtHrS6WvHU/qGsb4GlPGKfyR2f2dxr5stXtF331VY5ZvDkWqe40Alo/f?=
	=?utf-8?q?vuTgz9avwy9QS6OWLJ5FOHbXSi3A2iMVj0LS2lgBBf6HQmX60TNeCu+ikrgZY0Tq9?=
	=?utf-8?q?5R7VGicCBMFeoiY4lDFHSTfmpO6Gs32xtI9Nf/boYZdgvUQozV6cwdZvY4Oc7n633?=
	=?utf-8?q?f4s1Kw6uy3aVlx5jjxmTfhcFiahJZXT06gg=3D=3D?=
X-Forefront-Antispam-Report: 
	CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU0PR04MB9251.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(7416014)(376014)(366016)(1800799024);DIR:OUT;SFP:1101;
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?ijOup9jd2ZkHPt3LPqTWMp0Holc1?=
	=?utf-8?q?QNI8vc+Wq+OX9xs/nt//Ku2T33oJFPWR0Zoj/hsfFZqLJbvn7GJEik/XL+8mZBPWk?=
	=?utf-8?q?qcoxowWwU0yFT+Ze2MCJcwYvoSyL0dC6ADuAUPRV3vSlltEGEYPH8eW01jj4KYPiy?=
	=?utf-8?q?HHpqB+yO6hsi3+4zMT6WvgPomVbG4TZX7/jNn0E+BaIkwnIDaXqahjQuhQ31jlArr?=
	=?utf-8?q?sLT1QRWc7vIFn+ziAVLL8PyVYKSxt1UBYPU3vAF01c+D36RTOIV+AQ32rbNV0na7y?=
	=?utf-8?q?+gKhzRZVx9iIqKGEE788PaoMlS27HriCoNxJI+s55GvhosALl0aN71XeBINWnlYJh?=
	=?utf-8?q?2SMzsvLhuj0tmPwFN6vuEB1ElqtQiZWgxjywOt5sNfT0J/jZAS9iaIWAWbiWPEO2+?=
	=?utf-8?q?AqFZaJs1028Z86q8gxez2DBNYyppb3B/pMXhobcKA5cLVnfRmIT/Q3fe9V/CkGgE7?=
	=?utf-8?q?ex6SWZlpOEeGPA0JbuMin7Y9AyzT8xGa7YS40Wkr1M5KH+PwMhEbyTdImZkCtnhS8?=
	=?utf-8?q?HBXGLr+z432oNZq/u6QbGVfZwx993zhNYBuydYUd5GiijUhtDt/wU8yIHxCqpM2H8?=
	=?utf-8?q?pWPZEALL/1AXV399DhE4ITzEGFVAgusZofL6XGJYnp6+JaK5aP8QpxgeJG/KlIl1L?=
	=?utf-8?q?vrHMKoYHzIXTlj0uQ2uHKya4GZuPFWqa1uO6qlJTzEz66mG6KewD5bHzFZwaHfv8p?=
	=?utf-8?q?/Imw96idXD9xD2Oj3fjYpkaA5hbbHxJln9aI1FLGH8r7BjiRnUBWoQLiJf3tOhr/E?=
	=?utf-8?q?GrWR4cyKHmu3PgI3Aq3k2z4tVO02JdOc3Q5UQrmg95Df3CPLzB3DvUSYu7tqjB+u2?=
	=?utf-8?q?4kF8/qmeK/IAYtRjIANPmQCIrVRJoGiAIKJ6ygT3hV6nqNkVdwwp8g8vVkgC6KZn9?=
	=?utf-8?q?iq9zELHiEat4hubsYM6sumN4G0xcC5y1ZvW0K/+4pia6SZ3/LIYHsclDiFlVg+qhJ?=
	=?utf-8?q?fnCt5rSK4xiVc86v7bEKtmKI0nCRvS4fZUEhD4tM+wpc01opAQTambi+dsohWsr4q?=
	=?utf-8?q?o7T4TlMlgqWxPzg+5YyUbtqJgbb+jXsiC1N+aJmrBOY9/M43Fat0QSrym0/ylZt1g?=
	=?utf-8?q?xeU6hq5u26QuHSzen4wyNUfXRlhJnD4IVfOWFYlOdSkQOGNO2w8M3MRnQqrXh9VlI?=
	=?utf-8?q?c/vQmBRwsnjkXM64iOR/+UqiOY+N/IKH4KXgLImrXYpSa5Yr4aZV31dqDWIhR66Ft?=
	=?utf-8?q?GpwgV5G/W7CZwjufwf7GG4pqBP1Pq50+GtY6m9cVyxyhwG4NDAuOgvbJCOORqmWD3?=
	=?utf-8?q?UxTuORvjTlVXvLxaXHoTWVX/AvFNXuTND0sNHupQaXpSr1vGkY/4sTA2Nf4i1ZaEn?=
	=?utf-8?q?pkSrv/IUjDIikDfKmR5ooF8pBN13ZWZcD0hWvxV4QZJhOnut5sPCaDbMo0othjyBL?=
	=?utf-8?q?wBiE+8DaSLh/0EpCJFLqKeUDTEpTqYAg8eZChWPwhp1PcjDmFdl8jJUZpZpFvS22r?=
	=?utf-8?q?SW/T+pDd+Ja8mY6hJ4D1ZoUjHzCnDVmEoVbytsMq23dpQ5NWcXvyBEKvSxPkhOIsY?=
	=?utf-8?q?VuYlWVG5uqYeBMB4oYoj1D6Bvlu3DNsKdw=3D=3D?=
X-OriginatorOrg: oss.nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 
 a985112a-1e20-40fb-12e2-08dcdca2f91f
X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9251.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Sep 2024 14:12:50.5403
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: 
 ZyrdFkqiWsY48p7IKFXXTZjcGA1mHCzMs4LfxvU1Xc+W8Xl0GXwNWpIJ9FrncQnRj4oKM7cLaV0DkF43UrNy9XU7Q+T5l7eiZ8NcI6F2Kqw=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB9791

Series

add NXP LINFlexD UART clock support for S32G2/S32G3 SoC | expand

Message

Ciprian Marian Costea Sept. 24, 2024, 2:12 p.m. UTC

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

LINFlexD UART driver is used by S32 SoC family.
Add clocking support as optional in order to not break
existing support for S32V234 SoC.

A separate patch adding clock definitions to
the S32G2/S32G3 based boards devicetree will be sent
for review.

Ciprian Marian Costea (2):
  dt-bindings: linflexuart: add clock definitions
  serial: fsl_linflexuart: add clock support

 .../bindings/serial/fsl,s32-linflexuart.yaml  | 21 ++++++
 drivers/tty/serial/fsl_linflexuart.c          | 67 ++++++++++++++-----
 2 files changed, 72 insertions(+), 16 deletions(-)