From patchwork Mon May 12 11:53:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2lyaXVzIFdhbmcgKOeOi+eak+aYsSk=?= X-Patchwork-Id: 889606 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD0919443; Mon, 12 May 2025 11:54:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747050861; cv=none; b=jyUH/agXgCb8PxOTIe13faJZM/Qq/ce6JdEli2A3/f11ckP22hddTfW0yBaT64QqA9i/njOfN7bSLeEvkPxjNmsVqfRs1hNqjcyJCL9waSfvychZGLjJp6v5cCWwD3hW0zdwjdIP9cO5LTFMoshEylMyBSHLaZUSi6YH82zIRMc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747050861; c=relaxed/simple; bh=yoCr8Cw7ciWuvaGQmZFA8dVvKMkIHB9m6FCuH2oE/l0=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=M0Y6PFmwJaz+ea/Dqyh/X7gn60XUhNSgz/hJmZIbIA56JX4NOjyOaOXeqJ7QKtZyROKpCC3TDmVhLo+yA1LQw1UQUGda/GZtexcKNeSKpIqu442uRh7e73O8RSk8uJ7o58Mp2TqkZ4JxbBRXfvjqLG9FOy9akZobcLs9IGqN138= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=RZyazV4/; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="RZyazV4/" X-UUID: ccf1cb782f2711f082f7f7ac98dee637-20250512 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=vavH7lvXqySuJa+hx0NcjRm6IStTczVgtkHsC8BjBGw=; b=RZyazV4/RyTPi/+5WH+QsjjRG0t6Fq77Pp683SyPVctZr6OfP978f0/nL2oVIDk6E9ZHtTNoix+UAbmkFeH+v9xzRxZ9p4UGMra/roJAx76iIBtj1seQzTgBe+v+efoGB7gkzT9GgUGSZoqIPe4n62B6ABDxP5kNPKFXMxGr/HI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1, REQID:3ec886dc-fd60-4353-b08d-64741768f283, IP:0, UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f, CLOUDID:9ab09db7-5e6b-4d0f-a080-a5e9cb36bea6, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0|50,EDM:-3,IP:ni l,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ccf1cb782f2711f082f7f7ac98dee637-20250512 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 347709756; Mon, 12 May 2025 19:54:03 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 12 May 2025 19:54:00 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 12 May 2025 19:54:00 +0800 From: Sirius Wang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Jiri Slaby , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang CC: , , , , , , , Sirius Wang Subject: [PATCH v3 0/3] Add mt8189 dts evalution board and Makefile Date: Mon, 12 May 2025 19:53:47 +0800 Message-ID: <20250512115355.923342-1-sirius.wang@mediatek.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 We add basic chip support for Mediatek MT8189 on evalution board. In this series, we also add dt-bindings document definition for MT8189. This series is based on tag: next-20250509 Changs in v3: - Move ulposc and ulposc3 before cpu nodes. - Refactor cpu-map to a single cluster0. - Change cpu nodes name from medium core to big core. - Move psci before timer nodes. Changs in v2: - Fix warning issues for make CHECK_DTBS=y - Add mediatek,uart.yaml document Sirius Wang (3): dt-bindings: arm: Add compatible for MediaTek MT8189 dt-bindings: serial: mediatek,uart: Add compatible for MT8189 arm64: dts: mt8189: Add mt8189 dts evaluation board and Mafefile .../devicetree/bindings/arm/mediatek.yaml | 4 + .../bindings/serial/mediatek,uart.yaml | 1 + arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8189-evb.dts | 20 + arch/arm64/boot/dts/mediatek/mt8189.dtsi | 427 ++++++++++++++++++ 5 files changed, 453 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8189.dtsi Acked-by: Conor Dooley