Toggle navigation
Patchwork
linux-serial
Patches
Bundles
About this project
Login
Register
Mail settings
Show patches with
: Submitter =
Shenwei Wang
| Archived =
No
| 11 patches
Series
Submitter
State
any
Action Required
New
Under Review
Accepted
Rejected
RFC
Not Applicable
Changes Requested
Awaiting Upstream
Superseded
Deferred
Search
Archived
No
Yes
Both
Delegate
------
Nobody
andy.doan@linaro.org
andy.doan@linaro.org
Apply
Patch
Series
S/W/F
Date
Submitter
Delegate
State
[v5,1/1] tty: serial: fsl_lpuart: optimize the timer based EOP logic
[v5,1/1] tty: serial: fsl_lpuart: optimize the timer based EOP logic
-
-
-
2023-05-10
Shenwei Wang
Superseded
[v4,1/1] tty: serial: fsl_lpuart: optimize the timer based EOP logic
[v4,1/1] tty: serial: fsl_lpuart: optimize the timer based EOP logic
-
-
-
2023-05-09
Shenwei Wang
New
[v3,1/1] tty: serial: fsl_lpuart: optimize the timer based EOP logic
[v3,1/1] tty: serial: fsl_lpuart: optimize the timer based EOP logic
-
-
-
2023-05-08
Shenwei Wang
Superseded
[v2,1/1] tty: serial: fsl_lpuart: optimize the timer based EOP logic
[v2,1/1] tty: serial: fsl_lpuart: optimize the timer based EOP logic
-
-
-
2023-05-04
Shenwei Wang
Superseded
[1/1] tty: serial: fsl_lpuart: optimize the timer based EOP logic
[1/1] tty: serial: fsl_lpuart: optimize the timer based EOP logic
-
-
-
2023-05-02
Shenwei Wang
Superseded
[1/1] tty: serial: fsl_lpuart: adjust buffer length to the intended size
[1/1] tty: serial: fsl_lpuart: adjust buffer length to the intended size
-
-
-
2023-04-10
Shenwei Wang
New
[1/1] serial: fsl_lpuart: fix RS485 RTS polariy inverse issue
[1/1] serial: fsl_lpuart: fix RS485 RTS polariy inverse issue
-
-
-
2023-02-07
Shenwei Wang
New
[v2,1/1] serial: fsl_lpuart: RS485 RTS polariy is inverse
[v2,1/1] serial: fsl_lpuart: RS485 RTS polariy is inverse
-
-
-
2022-08-05
Shenwei Wang
Superseded
[1/1] serial: fsl_lpuart: RS485 RTS polariy is inverse
[1/1] serial: fsl_lpuart: RS485 RTS polariy is inverse
-
-
-
2022-08-02
Shenwei Wang
Superseded
[V1,1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
[V1,1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
-
-
-
2022-07-08
Shenwei Wang
New
[1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
[1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
-
-
-
2022-07-08
Shenwei Wang
Superseded